关键词： 多处理器系统   性能分析   扩充Petri网   模型分析   马尔可夫链   建模机制   GSPN模型  

摘要： Petri网作为离散事件系统建模、性能分析及控制的数学图形工具 ,已有广泛应用。本文介绍扩充Petri网及其在多处理器系统性能分析中的应用。

关键词： crossbar switches   cache architectures   scalable interconnects   wormhole routing   shared memory multiprocessors   execution-driven simulation  

摘要： Cache coherent nonuniform memory access (CC-NUMA) multiprocessors provide a scalable design for shared memory. But, they continue to suffer from large remote memory access latencies due to comparatively slow memory technology and large data transfer latencies in the interconnection network. In this paper, we propose a novel hardware caching technique, called switch cache, to improve the remote memory access performance of CC-NUMA multiprocessors. The main idea is to implement small fast caches in crossbar switches of the interconnect medium to capture and store shared data as they flow from the memory module to the requesting processor. This stored data acts as a cache for subsequent requests, thus reducing the need for remote memory accesses tremendously. The implementation of a cache in a crossbar switch needs to be efficient and robust, yet flexible for changes in the caching protocol. The design and implementation details of a CAche Embedded Switch ARchitecture, CAESAR, using wormhole routing with Virtual channels is presented. We explore the design space of switch caches by modeling CAESAR in a detailed execution driven simulator and analyze the performance benefits. Our results show that the CAESAR switch cache is capable of improving the performance of CC-NUMA multiprocessors by up to 45 percent reduction in remote memory accesses for some applications. By serving remote read requests at various stages in the interconnect, we observe improvements in execution time as high as 20 percent for these applications. We conclude that switch caches provide a cost-effective solution for designing high performance CC-NUMA multiprocessors.

关键词： 非模块型   人工神经网络   并行实现   多处理器  

摘要： 本文对两种非模块型神经网络——全连接和随机连接神经网络在多处理器网络上并行实现的性能进行了分析 ,指出处理器网络的拓扑结构和结点的扇入对这两种神经网络的并行实现的性能影响不大 ,并对神经网络在多处理器网络上并行实现时一个学习周期时间进行了分解 。

关键词： 数控机床   经济型数控系统   多任务并行处理   数控模型   插补缓冲区  

摘要： 该文主要利用多任务并行处理技术的思想研究以通用微机为控制核心的数控模型、软件技术,同时对适合于经济型数控系统的调整高精度的插补算法、速度控制和闭环原理、加工过程仿真和动态显示技术等做了较为深入的研究.作者首先研究了多任务并行处理技术在数控领域的应用原理,建立了适合于单CPU的基于高速插补缓冲区的数控模型.作者接着对数控基本控制功能进行了深入的研究,分别提出了一种基于最小偏差原理的快速、高精度、适用性强的通用曲线直接插补方法,变频加速度升降速控制理论,以及适合于经济型数控系统的基于插补缓冲区的闭环控制方法,提高了经济型数控系统的加工性能和效率.作者随后对数控加工过程的动态显示和仿真技术进行了研究,提出了数据、图形分割法,结构化的数控加工程序结构体系,以及NC加工程序预编译技术,为实现加工过程的仿真和动态显示打下了基础.最后,在大量研究的基础上,利用面向对象的Borland C++程序设计语言,应用面向对象的程序设计(OOP)方法,研究开发MNC-CXZ300经济型数控多功能机床加工系统,该系统界面友好,使用方便,功能全面,可移植性好,通用性强,适用范围广,不仅可用于实际加工生产,而且还可用于数控教学和培训,最适合中国国情,符合数控技术发展最新方向的新一代MNC经济型数控系统.

关键词： 现场总线   多处理器   LONWORKS网络   分布式控制  

摘要： 在基于 L ONWORKS网络的现场总线中 ,Neuron芯片是节点的核心 ,但是其处理能力不足以胜任复杂的计算任务 .为增强节点的计算能力 ,提出并实现了一种非对称多处理器 (AMP)结构的控制节点设计方案 ,多个处理器之间采用共享总线相连 ,Neuron芯片为主处理器 ,3个从处理器并行完成信号的高速采样计算 .在具体实现中 ,提出了单缓冲、双通道总线、两级树状网络、通信线程细化等技术手段 .

关键词： parallel processing   software environment   synchronous communication   clustering algorithm   distributed application   deadlock  

摘要： A variety of techniques and tools exist to parallelize software systems on different parallel architectures (SIMD, MIMD). With the advances in high-speed networks, there has been a dramatic increase in the number of client/server applications. A variety of client/server applications are deployed today, ranging from simple telnet sessions to complex electronic commerce transactions. Industry standard protocols. like Secure Socket Layer (SSL), Secure Electronic Transaction (SET), etc., are in use for ensuring privacy and integrity of data, as well as for authenticating the sender and the receiver during message passing. Consequently, a majority of applications using parallel processing techniques are becoming synchronization-centric, i.e., for every message transfer, the sender and receiver must synchronize. However, more effective techniques and tools are needed to automate the clustering of such synchronization-centric applications to extract parallelism. In this paper, we present a new clustering algorithm to facilitate the parallelization of software systems in a multiprocessors environment. The new clustering algorithm achieves traditional clustening objectives (reduction in parallel execution time, communication cost, etc.). Additionally, our approach 1) reduces the performance degradation caused by synchronizations, and 2) avoids deadlocks during clustering. The effectiveness of our approach is depicted with the help of simulation results.

关键词： CPU   RISC   微处理器   多处理器系统  

摘要： 多个ＲＩＳＣＭ处理器构成的对称多处理器系统正在成为多机并行系统的主流产品。在对称多处理器系统中，所有处理器的地位都是相同的，所有的系统资源都具有相同的可访问性，系统依据仲裁算法自动调度处理器访问控制权。通过分析当前多处理器系统的代表机型Ｓｐａｒｃ２０的加电自检程序，对多机系统的处理器转换机制进行了研究，给出了其切换时机和实现过程的算法描述。

关键词： 神经网络   并行实现   性能分析   多处理器  

摘要： 直觉告诉我们:当人工神经网络算法在多处理器系统上并行实现时,处理器网络的拓扑结构和处理器节点的扇入尺寸(即输入输出规模)会影响并行算法的效率,但是对全连接和随机连接神经网络,上述结论并不成立。在神经网络的并行实现中,处理器的通信开销是一个主要的限制因素,本文将对全连接和随机连接神经网络并行实现的几个相关问题进行讨论。1

关键词： parallel algorithms   parallel architectures   locality  

摘要： The Vector Multiprocessor brings to the multiprocessor what vectorization brought to the single processor. In addition to the usual complement of logic and arithmetic units, each processor contains a programmable communication unit with registers that communicate directly with comparable registers in neighboring processors via an n-dimensional interconnection network. Interprocessor communication tasks are performed to and from these registers in the same way that computational tasks are performed on a vector uniprocessor. Communication is shown to be optimal for a large class of communication tasks. Elements are transmitted, in parallel, to their destination processors at an average rate of one per communication cycle. This result, called O(1) access, is used to develop a balanced communication system where local and global access are comparable. It is also used to support the "vector parallel paradigm" where all arrays are uniformly distributed and the user interface "looks" like a vector uniprocessor interface. Both coarse- and fine-grain performance models are provided, which demonstrate the unexpected result that communication is asymptotically negligible compared to computational time. Finally, three performance models are presented for the spherical harmonic transform, which is the most communication-intensive part of climate model dynamics.

关键词： digital signal processor   multiprocessing systems   multiprocessor interconnection   split-transaction bus  

摘要： An MIMD multiprocessor digital signal- processing (DSP), chip containing four 64-b processing elements (PE's) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a,32-6 RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PE's are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory;multiprocessing using a modified-MESI data coherency protocol, High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PE's. Process synchronization is achieved using cached semaphores. The 200-mm(2), 0.25-mu m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply.