关键词： .crossbar   Rapid Prototyping   data routing   Reconfigurable Multiprocessor   DSP Data   instruction bandwidth   megabytes  

摘要： A field-programmable multiprocessor integrated circuit, PADDI (for Programmable Arithmetic Devices for High-Speed Digital Signal Processing), has been designed for the rapid prototyping of high-speed data paths typical to real-time digital signal processing applications. The processor architecture addresses the key requirements of these data paths: a) fast, concurrently operating, multiple arithmetic units, b) conflict-free data routing, c) moderate hardware multiplexing (of the arithmetic units), d) minimal branch penalty between loop iterations, e) wide instruction bandwidth, and f) wide I/O bandwidth. The initial version contains eight processors connected via a dynamically controlled crossbar switch, and has a die size of 8.9 X 9.5 mm2, in a 1.2-mum CMOS technology. With a maximum clock rate of 25 MHz, it can support a computation rate of 200 MIPs and can sustain a data 1/O bandwidth of 400 megabytes/s with a typical power consumption of 0.45 W. An assembler and simulator have been developed to facilitate programming and testing of the chip. A software compilation path from the high-level data flow language SILAGE [15] to PADDI is currently under development, and handles partitioning, scheduling, and code generation.

关键词： 并行处理   计算机系统   软件  

摘要： Task scheduling is one of the most important issues in a hard real-time system, because it is the schedule that ensures tasks meet their deadlines and precedence constraints. Given a set of hard real-time tasks, to determine whether a feasible schedule exists such that the timing constraints and precedence constraints of the tasks are satisfied, and to produce such a schedule if one exists are the purposed of a static scheduler. The previous work done for the static scheduler in the computer aided prototyping system (CAPS) was mainly for the single processor environment. The major work of this thesis is to develop several algorithms for scheduling hard-real-time tasks on multiprocessor systems so that the associated timing and precedence constraints, as well as the communication requirements are met under the worst-case scenario.

关键词： 多处理器   计算机系统   硬件   并行  

关键词： 处理器   放大   嵌入式   设计  

摘要： 当前的VME卡盒中的千兆级翻转(Gigaflop)性能可能归功于Mercurry Compute-System公司的板级多处理器设计。采用4个i860处理器在9UVME卡上使用模块就可以作成MC860VS单板机(见图)。每一个处理卡能够运行到320MFLops,在一个以耦合处理的环境中,VME总线上可以具有高达8个的MC860 VS板,32个i860这一最大模式提供了2.5GFLops的最大处理能力。

关键词： 计算机   并行处理技术   同步  

摘要： 同步是一种为了保证相互协作的多个迭代按正确顺序执行,以获得与串行结果相同的技术。如果并行算法的一个迭代过程在交互点处需要等待其它迭代过程运行结束,称这个点为同步点。具有同步点的并行算法称为同步算法。由于在同步点处将出现等待,因而同步的出现将影响多处理器并行算法的运行效率,故在并行算法的构造中,应尽量减少同步点的设置。但对一个大的实际问题来说,同步又是很难避免的。本文即针对有并发循环存在的多处理机系统中所出现的同步问题展开讨论。它涉及到同步的基本概念,同步的探测,数据相关性,同步的建立与退出等一系列问题,这些是进一步研究同步策略与方法的重要基础。

关键词： 模拟   并行性   EcliPSe系统  

关键词： GARBAGE COLLECTION   LOCK-FREE ALGORITHMS   MEMORY MANAGEMENT   MULTIPROCESSORS   SHARED MEMORY   WAIT-FREE ALGORITHMS  

摘要： Garbage collection algorithms for shared-memory multiprocessors typically rely on some form of global synchronization to preserve consistency. Such global synchronization may lead to problems on asynchronous architectures: if one process is halted or delayed, other, nonfaulty processes will be unable to progress. By contrast, a storage management algorithm is lock-free if (in the absence of resource exhaustion) a process that is allocating or collecting memory can be delayed at any point without forcing other processes to block. This paper presents the first algorithm for lock-free garbage collection in a realistic model. The algorithm assumes that processes synchronize by applying read, write, and compare&swap operations to shared memory. This algorithm uses no locks, busy-waiting, or barrier synchronization, it does not assume that processes can observe or modify one another's local variables or registers, and it does not use inter-process interrupts.