摘要： Dynamic systems have grown to enormous size and complexity. The ability to simulate the systems has greatly helped in the design and op- eration of these systems. Inspite of advancements in model simplification techniques and refinements in solution procedures, many of todays systems are prohibitively expensive to simulate with the required accuracy. It was felt that the equations describing the system could be solved in paral- lel with savings in computer time. To this end the solution process was studied to find large scale (macro) parallelism. Macroparallelism was found both in the equations of the model and in the solution processes. Once this parallelism was found, requirements for and gains achievable by multiprocessors which use this inherent parallelism were developed. An efficient set of model equations is obtained by converting the differential equations to algebraic equations by the implicit multi-step integration fomulas. The entire set of equations is then solved by an iterative algorithm. The Chaotic Relaxation and Newton-SOR Algorithms exhibit a high degree of parallelism which can be increased by ordering the equations to the near block diagonal form. This ordering is possible because of the sparsity present in models of large systems. The Gauss- Seidel and true Newton Algorithms are not obviously executable in parallel, but by ordering the equations to a bordered block diagonal form parallelism is exposed. The requirements for sharing data are dictated by the form of the equations, while the control requirements depend on the algorithms. The near block diagonal form algorithms exchange solution data through shared memory, and it is the contention over this shared memory which limits the gains achievable by parallel execution. Simple high order multiproces- sors can efficiently execute the Chaotic Relaxation and Newton-SOR Al- gorithms. The bordered block diagonal form algorithms require that the processors solving the diagonal blocks alternate activ

关键词： NA  

关键词： Aeronautics and Astronautics  

摘要： In this thesis the synchronization requirements of a fault-tolerant multiprocessor are defined and methods of main- tenance of synchronism are developed. It is demonstrated that a synchronous fault-tolerant multiprocessor driven by. a fault- tolerant clock is more efficient and more easily impleinented than is an asynchronous fault-tolerant multiprocessor. Fault-tolerant clocking has been examined intensively here. From fault-tolerance requirements and the established multiprocessor synchronization requirements, general specifi- cations are developed for a fault-tolerant clock. Two general methods of design have been explored, and it has been concluded that if the clock is to be distributed to many modules, fault- tolerant clocking through the concepts advanced by William Daly and John McKenna of the C. S. Draper Laboratory, is more practi- cal to implement than is fault-tolerant clocking through failure- detection and subsequent clock substitution. Clocks developed by Daly and McKenna have been examined, refined, and revised. It is demonstrated that it is desirable to have available a fault-tolerant clock which runs at 20 MHz, but that such a frequency is not achieveable by a McKenna-type clock (with use of current technology). A method of achieving the use of a relatively slow McKenna-type clock in conjunction with a fre- quency multiplier is developed. Also, analog phase-locking techniques are shown to be unsuitable for the design of a fault- tolerant clock.

关键词： 无故障   平均   时周   静算   磁心   军用计算机   军事领域用计算机   多处理器   续表   变址   字长   微程序   软件  

摘要： 这篇概述性文章提供了一张内容广泛的军用计算机和加固型计算机的表格以及对它们的讨论,这些计算机一般在布场上都有。本文的另一目的是对一般读者提供一些技术知识,由于商用计算机的制造者试图生产更可靠的计算机,这种知识就成为颇为普通的了。本文包括许多使用中规模集成电路和大规模集成电路的计算机。

摘要： As multiprocessing becomes increasingly successful in scientific and commercial computing. parallel systems will be subjected to increasingly complex and challenging workloads. T ensure good job response and high resource utilization, algorithms are needed to allocate resources to jobs and to schedule the jobs. This problem is of central importance, and pervades systems research a.t diverse places such as compilers, runtime, applications, and operating systems. Despite the attention this area has received, scheduling problems in practical parallel computing still lack satisfactory solutions. The focus of system builders is to provide functionality and features; the resulting systems get so complex that many models and theoretical results lack applicability. The focus of this thesis is in between the theory and practice of scheduling: it includes modeling, performance analysis and practical algorithmics. We present a variety of new techniques for scheduling problems relevant to parallel scientific computing. The thesis progresses from new compile time algorithms for message scheduling th rough new runtime algorithms for processor scheduling to a unified framework for allocating multiprocessor resources to competing jobs while optimizing both individual application performance and sstem throughput.

摘要： Shared-memory multiprocessors offer increased computational power and the programmability of the shared-memory model. However, sharing memory between processors leads to contention which delays memory accesses. Adding a cache memory for each procssor reduces the aver- age access time, but it creates the possibility of inconsistency among cached copies. The cache coherence problem is keeping all cached copies of the same memory location identical. This disser- tation explores possible solutions to the cache coherence problem and identifies cache coherence protocols-solutions implemented entirely in hardware-as an attractive alternative. Protocols for shared-bus systems are shown to be an interating special case. Previously pro- posed shared-bus protocols are described using uniform terminology, and they are shown to divide into two categories: invalidation and distributed write. In invalidation protocols all other cached copies must be invalidated before any copy can be changed; in distributed write protocols all copies must be updated each time a shared block is modified. In each category, at new protocol is presented with better performance than previous schemes, based on simulation results. The simulation model and parameters are described in detail. Previous protocols for general interconnection networks are shown to contain flaws and to be costly to implement. A new class of protocols is presented that ofiers reduced implementation cost and expandability. while retaining a high level of performance, as illustrated by simulation results using a crossbar switch. All new protocols have been pro'-/en correct; one of the proofs is included. Previous definitions of cache coherence are shown to be inadequate and a new definition is presented. Coherence is compared and contrasted with other levels of consistency, which are also identified. The consistency of shared-bus protocols is shown to be naturally stronger than that of non-bus protocols. The first protocol of its kind is

摘要： Modern embedded systems must increasingly accommodate dynamically changing operating environments, high computational requirements, exibility (e.g., for the emer- gence of new standards and services), and tight time-to-market windows. Such trends and the ever-increasing design complexity of embedded systems have challenged design- ers to raise the level of abstraction and replace traditional ad-hoc approaches with more efcient synthesis techniques. Additionally, since embedded multiprocessor systems are typically designed as nal implementations for dedicated functions, modications to em- bedded system implementations are rare, and this allows embedded system designers to spend signicantly larger amounts of time to optimize the architecture and the employed software. This dissertation presents several system-level synthesis algorithms that employ thorough and hence time-intensive optimization techniques (e.g. evolutionary algorithms) that allow the designer to explore a signicantly larger part of the design space. It looks at critical issues that are at the core of the synthesis process selecting the architecture, partitioning the functionality over the components of the architecture, and scheduling ac- tivities such that design constraints and optimization objectives are satised. More specically for the scheduling step, a new solution to the two-step (cluster- ing and cluster-merging) multiprocessor scheduling problem is proposed. For the rst step or pre-processing step of clustering a simple yet highly efcient genetic algorithm is proposed. Several techniques for the second step of merging or cluster scheduling are proposed and nally a complete two-step effective solution is presented. Also, a randomization technique is applied to existing deterministic techniques to extend these techniques so that they can utilize arbitrary increases in available optimization time. This novel framework for extending deterministic algorithms in our context allows for accurate and f

关键词： 多处理器   目标检测   视频跟踪   并行系统   multi processors   object detecting   video tracking   parallel system  

摘要： 传统视频跟踪系统的目标检测环节常采用手动指定或使用单处理器运算来确定跟踪目标,这种方法耗费人力且检测速度慢。针对此问题提出了一种改进的图像分割方法,该方法采用多处理器系统构架,并行处理分割区域,增加了检测目标的速度,并且在后续目标跟踪环节中,各处理器根据任务划分,协同处理跟踪任务。实验结果表明基于多处理器系统构架的视频跟踪系统能够实现快速自动检测与跟踪目标,系统加速比为2.066,处理器效率为51.65%。关键词

摘要： The continued march of technological progress, epitomized by Moore's Law provides the microarchitect with increasing numbers of transistors to employ as we continue to shrink feature geometries. Physical limitations impose new constraints upon designers in the areas of overall power and localized power density. Techniques to scale threshold and supply voltages to lower values in order to reduce power consumption of the part have also run into physical limitations, exacerbating power and cooling problems in deep sub-micron CMOS process generations. Smaller device geometries are also subject to increased sensitivity to common failure modes as well as manufacturing process variability. In the face of these added challenges, we observe a shift in the focus of the industry, away from building ever-larger single-core chips, whose focus is on reducing single-threaded latency, toward a design approach that employs multiple cores on a single chip to improve throughput. While the early multicore era utilized the existing single-core designs of the previous generation in small numbers, subsequent generations have introduced cores tailored to multicore use. These cores seek to achieve power-efficient throughput and have led to a new emphasis on throughput-oriented computing, particularly for Internet workloads, where the end-to-end computational task is domi- nated by long-latency network operations. The ubiquity of these workloads makes a compelling argument for throughput-oriented designs, but does not free the microarchitect fully from latency demands of common workloads in enterprise and desktop application spaces. We believe that a continued need for both throughput-oriented and latency-sensitive processors will exist in coming generations of technology. We further opine that making effective use of the additional transistors that will be available may require different techniques for latency-sensitive designs than for throughput-oriented ones, since we may trade latency o

摘要： Efficient multiprocessing approaches to the execution of digital computer programs, which analyse power system transient stability, have been investigated. Different program sections are found to have greatly varying levels of effect on overall execution performance. The most demanding need which emerges is for a very efficient practical method to solve large sparse sets of linear equations. Without a satisfactory scheme, the maximum gain in performance over single processor operation is severely restricted. A suitable algorithm has been developed and is described. To validate the effectiveness of proposed algorithms, practical multiprocessing hardware has been built. The equipment has also allowed evaluation of hardware requirements, in particular the capability of the inter-processor communication network. The parallel processor developed enables efficient program development and testing in an environment which is research oriented yet very closely resembles possible practical implementations. The results of an execution simulation are combined with practical performance measurements to determine limits to the number of processors usefully employed, and the gains in performance over single processor operation achieveable. When compared with other algorithms for solving linear equations, the one developed is shown to run very efficiently. To further improve performance, novel methods of mixing execution of the linear equation solutions and other sections of a transient stability analysis program have been practically implemented.