关键词： 异构多处理器   任务调度   粒子群优化算法   禁忌搜索  

摘要： 为提高异构多处理器任务调度的执行效率,充分发挥多处理器并行性能,提出一种基于粒子群优化的异构多处理器任务调度算法——FPSOTTS算法。该算法以求得任务最短完成时间为目标,首先通过建立新的编码方式和粒子更新公式实现粒子搜索空间到离散空间的映射,使连续的粒子群优化算法适用于离散的异构多处理器任务调度问题;同时通过引入禁忌算法进行局部搜索,克服粒子群算法的早熟收敛现象,避免陷入局部最优。实验结果表明,FPSOTTS算法的执行效率优于Min-min算法和遗传算法,有效地降低任务的执行时间。FP-SOTTS算法很好地解决了异构多处理器任务调度问题,并且适合于大规模并行任务调度。

关键词： Power capping   cache latency   fairness   performance differentiation   control theory   chip multiprocessors  

摘要： Limiting the peak power consumption of chip multiprocessors (CMPs) has recently received a lot of attention. In order to enable chip-level power capping, the peak power consumption of last-level (e. g., L2) on-chip caches in a CMP often needs to be constrained by dynamically transitioning selected cache banks into low-power modes. However, dynamic cache resizing for power capping may cause undesired long cache access latencies, and even thread starving and thrashing, for the applications running on the CMP. In this paper, we propose a novel cache management strategy that can limit the peak power consumption of L2 caches and provide fairness guarantees, such that the cache access latencies of the application threads coscheduled on the CMP are impacted more uniformly. Our strategy is also extended to provide differentiated cache latency guarantees that can help the OS to enforce the desired thread priorities at the architectural level and achieve desired rates of thread progress for coscheduled applications. Our solution features a two-tier control architecture rigorously designed based on advanced feedback control theory for guaranteed control accuracy and system stability. Extensive experimental results demonstrate that our solution can achieve the desired cache power capping, fair or differentiated cache sharing, and power-performance tradeoffs for many applications.

关键词： Fault tolerance  

摘要： Certain nodes cannot be faulty at the same time which can better reflect fault patterns in a real system than the existing ones. The determination of the size of a g-neighborhoods (i. e., a neighborhood of a set of g nodes) in a given graph is essential to analyze the fault tolerance of multiprocessor systems. In this paper, we present a novel fault tolerance measure for hypermesh based on the conditional components, proving the bounds of the neighborhoods of the conditional components and the other results related to fault tolerance. Our study results show that the originally corresponding results tend to underestimate resilience of interconnection multiprocessor systems. © 2012 Binary Information Press.

关键词： 任务复制   任务调度   多处理器   分簇复制  

摘要： 任务调度的优劣是决定并行分布式计算机系统性能好坏的重要因素之一。为优化任务调度,基于一些典型算法(如LG、PPA算法等),提出了一种新的任务调度算法。该算法一方面复制满足条件的前驱任务来缩短调度长度;另一方面合理地复制其他前驱任务和合并冗余簇来减少所需处理器的数目。实验表明,该算法在调度长度和所需处理器的数目上优于以上典型算法,并具有更小的时间复杂度,对并行计算机系统性能的提升具有一定的意义。

关键词： 双曲线边界   单调速率算法   首次适应分派策略   可调度性判定  

摘要： Lopez等学者求解出基于单调速率算法和首次适应分派策略的多处理器实时任务可调度性判定边界.该边界在所有O(m)复杂度的判定边界中是最优的.基于Bini等学者针对单处理器提出的双曲线可调度性判定方法,给出了一种多处理器实时任务可调度性判定边界.新边界在相当数量的利用率分布下明显优于已有边界.新边界与已有边界具有相容性,所以虽然新边界无法在所有情况下超越已有边界,但在实际应用中可联合两种边界进行判定,在不增加计算复杂度的同时全面提高可调度任务集的数量.

关键词： AXIS   集成软件   多处理器   GE   开发   版本   应用   总拥有成本  

摘要： GE智能平台近日发布AXIS（先进多处理器集成软件）开发环境的5.1版本,该软件适用于复杂、严苛环境的应用,如雷达、声纳和传感器处理等,5.1版本的推出使开发更加简单、快速,可极大降低项目风险和成本,并加快产品推向市场的时间。 AXIS,作为GE高性能嵌入式计算平台的关键组件,支持原型设计,可使内部研发的效用最大化。另外,该软件支持VSIPL开放标准API,可使其代码直接从当前CPU移植到下一代CPU中,从而降低总拥有成本。该产品支持VSIPL＋＋。

关键词： 片上多处理器   空间相关   时间相关   数据预取  

摘要： 片上多处理器中不同核的缺失地址序列之间通常存在一定的空间和时间相关性,为了充分利用该性质,本文提出时空结合的数据预取.该机制首先寻找核内缺失地址序列的相关性,在核内探索不到的情况下再寻找核间的相关性,因此可利用其它核的访存行为来预测本核可能即将发生的访存行为.实验结果表明,本文提出的数据预取机制可使测试程序的平均性能提高12.6%,与扩展应用在多核上的C/DC策略相比较,性能提高了3.8%.

关键词： Modeling   evaluation   design exploration   and optimization of multiprocessor systems   chip-multiprocessor architecture  

摘要： Beginning with Amdahl's law, we derive a general objective function that links parallel processing performance gains at the system level, to energy and delay in the subsystem microarchitecture structures. The objective function employs parameterized models of computation and communication to represent the characteristics of processors, memories, and communications networks. The interaction of the latter microarchitectural elements defines global system performance in terms of energy-delay cost. Following the derivation, we demonstrate its utility by applying it to the problem of Chip Multiprocessor (CMP) architecture exploration. Given a set of application and architectural parameters, we solve for the optimal CMP architecture for six different architectural optimization examples. We find the parameters that minimize the total system cost, defined by the objective function under the area constraint of a single die. The analytical formulation presented in this paper is general and offers the foundation for the quantitative and rapid evaluation of computer architectures under different constraints including that of single die area.

关键词： Out-of-order retirement   multicore processors   validation buffer   sequential consistency  

摘要： Out-of-order retirement of instructions has been shown to be an effective technique to increase the number of in-flight instructions. This form of runtime scheduling can reduce pipeline stalls caused by head-of-line blocking effects in the reorder buffer (ROB). Expanding the width of the instruction window can be highly beneficial to multiprocessors that implement a strict memory model, especially when both loads and stores encounter long latencies due to cache misses, and whose stalls must be overlapped with instruction execution to overcome the memory latencies. Based on the Validation Buffer (VB) architecture (a previously proposed out-of-order retirement, checkpoint-free architecture for single processors), this paper proposes a cost-effective, scalable, out-of-order retirement multiprocessor, capable of enforcing sequential consistency without impacting the design of the memory hierarchy or interconnect. Our simulation results indicate that utilizing a VB can speed up both relaxed and sequentially consistent in-order retirement in future multiprocessor systems by between 3 and 20 percent, depending on the ROB size.

关键词： 变电站自动化   控制保护系统   硬件平台   多处理器   高速总线  

摘要： 为适应IEC 61850和IEEE 1588等新技术在变电站自动化系统中应用的不断发展,必须设计新一代高性能、高可靠性的控制保护系统通用硬件平台。文中总结了控制保护硬件平台发展的过程,分析了目前大多数控制保护装置硬件的内部数据交互方式以及存在的不足,提出了基于分布式多处理器和模块化硬件架构的硬件平台设计,设计了一种分布式总线的通信架构,介绍了CPU模块、DSP模块和I/O模块的功能特点。基于该硬件平台的交直流控制保护系统已成功应用到多个变电站和直流输电工程中。