关键词： Image processing  

摘要： The single-mode algorithm cannot track the target stably because the characteristics of environment and targets are changing from time to time. As large field, high-resolution sensors are used, the realtime performance of the photoelectric measurement and tracking system is getting more and more important. So a multi-processor and multimode image tracking machine connected through Serial RapidIO(SRIO) was put forward. The target detecting in a single frame was realized by FPGAS and the target association and tracking were realized by DSPS. Based on the multimode image detecting and tracking technology, the main and assistant mode tracking technology and the contrast multi-feature association technology, the system can detect and track multi-target in real-time automatically. The experimental results indicate that the system could be suit for various environment and various targets which have different characteristics.

关键词： 实时系统   多处理器   节能调度   动态电压频率调节   动态功耗管理   绿色计算  

摘要： 嵌入式多处理器系统的能耗问题变得日益重要,如何减少能耗同时满足实时约束成为多处理器系统节能实时调度中的一个重要问题.目前绝大多数研究基于关键速度降低处理器的频率以减少动态能耗,采用关闭处理器的方法减少静态能耗.虽然这种方法可以实现节能,但是不能保证最小化能耗.而现有最优的节能实时调度未考虑处理器状态切换的时间和能量开销,因此在切换开销不可忽视的实际平台中不再是最优的.文中针对具有独立动态电压频率调节和动态功耗管理功能的多处理器系统,考虑处理器切换开销,提出一种基于帧任务模型的最优节能实时调度算法.该算法根据关键速度来判断系统负载情况,确定具有最低能耗值的活跃处理器个数,然后根据状态切换开销来确定最优调度序列.该算法允许实时任务在处理器之间任意迁移,计算复杂度小,易于实现.数学分析证明了该算法的最优性.

关键词： 单片机   分时操作系统   多任务   多处理器  

摘要： 设计了一个单片机分时操作系统,并给出其具体实现方式。该系统具有多任务定时切换及多处理器协同工作的功能,结构简单,资源占用少。

关键词： 簇总线   簇协调器   一致性冲突   外部一致性冲突   外部冲突解决  

摘要： 在基于MIPS R10000处理器构建采用簇总线的多处理器系统时,发现R10000用户手册给出的外部冲突解决方案只适用于采用专用EA的单或多处理器系统。鉴于此,介绍了R10000处理器的系统配置和系统接口的一致性,分析了R10000用户手册所给出的外部冲突解决方案的局限性,并基于该外部冲突解决方案,对采用簇总线的多处理器系统中的外部冲突进行了研究,给出了簇协调器可以采用的一个外部冲突解决方案。

关键词： 武汉华中数控股份有限公司   硬件体系结构   预览   展品   数控装置   总线技术   自主创新   多处理器  

摘要： 武汉华中数控股份有限公司 展位号：E1馆C203 HNC-848型总线式高档数控装置 HNC-848型总线式高档数控装置采用基于多处理器的开放式软硬件体系结构和自主创新的总线技术，硬件跨平台、软件可置换、系统多层次开放功能。

关键词： 动态管理视图   闩锁竞争   数据库性能  

摘要： 多处理器/多核系统在数据库服务器上的使用在提高了数据库并发处理能力的同时,但也使得一些在并发度不那么高的环境下没有暴露出来的问题得以显现,使用不当甚至反而降低实际的吞吐率.本文通过动态管理视图定位冲突点,解决闩锁竞争问题,大幅提升多处理器系统下SQL Server实际吞吐率,可以作为多处理器改善数据库服务性能的一个范例.

关键词： 片上多处理器   合作式Cache   非一致性访问   数据块复制迁移   Cache划分  

摘要： 片上多核技术的出现给处理器的设计和实现带来很多挑战,片上存储系统的设计就是其中最重要的方面之一.为了缓解日益严峻的存储墙问题,研究者们通常在片上放置大容量末级Cache,片上末级Cache设计和优化技术已成为当前的研究热点.介绍了片上多处理器(CMP)末级Cache设计面临的挑战,然后分别介绍了以私有设计和共享设计为基础的多种CMP末级Cache优化技术,并对它们进行了比较分析.

关键词： Redundancy  

摘要： To obtain the benefit of aggressive CMOS scaling, chip multiprocessors (CMP) has a tendency of integrating more processors on one chip. The increase of cores and voltage factors are increasing susceptibility of CMP to transient faults. To solve this problem, a lot of methods are proposed to enhance the fault tolerance ability of CMP. In these methods, coarse-grain thread-level redundancy (TLR) is more attractive because tolerating long verification latencies is supported. However, we observe that an external write operation not only results in memory inconsistency, but also induces redundancy coherence conflict. In this paper, based on relaxed input replication, we propose a fault-tolerant TLR, in which redundant threads maintain independent memory accesses and different coherence states of L2-cache line. Additionally, we compare three strategies in the use of simultaneous multithreading (SMT), which is another important design objective. Experiments are conducted on several parallel applications from the SPLASH-2, and the results show that the performance loss incurred is only 4% due to redundancy.

关键词： Cartesian product networks   cycle embedding   generalized hypercubes   nearest neighbor mesh hypercubes   pancycle problem   panconnectivity problem   path embedding  

摘要： In this paper, we consider two embedding problems in Cartesian product networks: one is the pancycle problem, which involves embedding cycles of various lengths in the given product network;and the other is the panconnectivity problem, which involves embedding paths of various lengths between any pair of distinct nodes in the given product network. We then apply our technical lemmas and theorems to derive new topological properties of two multiprocessor systems, namely, generalized hypercubes and nearest neighbor mesh hypercubes.

关键词： Multicore/single-chip multiprocessors   circuit-switching networks   cache memories  

摘要： Reducing data access latency is vital to achieving performance improvements in computing. For chip multiprocessors (CMPs), data access latency depends on the organization of the memory hierarchy, the on-chip interconnect, and the running workload. Several network-on-chip (NoC) designs exploit communication locality to reduce communication latency by configuring special fast paths or circuits on which communication is faster than the rest of the NoC. However, communication patterns are directly affected by the cache organization and many cache organizations are designed in isolation of the underlying NoC or assume a simple NoC design, thus possibly missing optimization opportunities. In this work, we take a codesign approach of the NoC and cache organization. First, we propose a hybrid circuit/packet-switched NoC that exploits communication locality through periodic configuration of the most beneficial circuits. Second, we design a Unique Private (UP) caching scheme targeting the class of interconnects which exploit communication locality to improve communication latency. The Unique Private cache stores the data that are mostly accessed by each processor core in the core's locally accessible cache bank, while leveraging dedicated high-speed circuits in the interconnect to provide remote cores with fast access to shared data. Simulations of a suite of scientific and commercial workloads show that our proposed design achieves a speedup of 15.2 and 14 percent on a 16-core and a 64-core CMP, respectively, over the state-of-the-art NoC-Cache codesigned system that also exploits communication locality in multithreaded applications.