关键词： Hardware-software codesign  

摘要： An embedded multiprocessor field programmable gate array (FPGA) system has a powerful and flexible architecture that the interaction between hardware circuits and software applications. Modern electronic products, such as portable devices, consumer electronics and telematics, can be evaluated rapidly in this platform via the implementation of a set of hardware and software tasks. However, the functionality is markedly increased, resulting in a significant raise in the number of hardware and software tasks. Consequently, too large of a solution space is formed to achieve hardware-software partitioning. Moreover, a partitioning result with low power consumption and fast execution time is difficult to obtain since meeting simultaneously multi-constraints from hundreds of thousands of combinations of hardware-software partitions is difficult. Thus, this work presents a hardware-software partitioning scheme that can obtain a partitioning result that satisfies multi-constraints from massive solution space. Specifically, this study attains a partitioning result with low power consumption and fast execution time. The effectiveness of the proposed approach is demonstrated by assessing a JPEG encoding system and a benchmark with 199 tasks.

关键词： Synchronous data transmission systems   Computer algorithms   Multiprocessors   Programming  

摘要： Synchronous Dataflow (SDF) is a widely-used model-of-computation for signal processing and multimedia applications. As Moore’s law comes to an end, multiprocessor systems are becoming ubiquitous in today’s embedded systems design. In this thesis, I address the problem of mapping a Homogeneous Synchronous Dataflow (HSDF) graph onto a multiprocessor platform with the objective of maximizing system throughput. The hardware platform consists of multiple processors connected with a communication substrate with guaranteed inter-processor communication latency, e.g. a hard real-time Network-on-Chip. Since the problem is a NP-hard combinatorial optimization problem, it is generally infeasible to use exhaustive search to obtain optimal solutions for realistic-sized applications. In this thesis, I adopt Genetic Algorithms, to search the design space of all possible actor-to-processor mappings and actor orderings on each processor to find the optimal solution, and compare the performance and scalability of GA with the exact solution technique based on SAT solving.

关键词： 智能平台   GE Fanuc   嵌入式系统   计算机系统   多处理器  

摘要： 以提供高端嵌入式产品的GE Fanuc智能平台近年来不断向市场推出了许多嵌入式硬件、软件及解决方案。2009RTECC展会上,其嵌入式系统部市场经理周辉先生表示,目前GE Fanuc智能平台逐渐发展为嵌入式领域产品线最丰富、最全面的厂商,其完善的产品线,既有非常高端的

关键词： 低功耗   高性能计算系统   并行计算   资源分配   作业管理   模拟  

摘要： 当前，高性能计算被广泛应用于高科技研究和诸多工业领域，以高性能计算为基础的计算科学得到了显著的发展。同时，需求的不断增加和对性能的苛刻要求给新一代的高性能计算系统的研究与设计带来了严峻的挑战。特别是随着处理器性能和系统规模的迅速提升，急剧增长的功耗严重限制了高性能计算系统的设计和使用。为有效管理系统功耗，提高系统的可靠性和可用性，最终降低高性能计算系统的拥有代价，低功耗技术已成为高性能计算领域的关键技术。 上世纪90年代以来，大规模并行处理系统（massively parallel processing，MPP）和集群（Cluster）系统已成为高性能计算机主要的体系结构。在并行计算系统中，并行资源管理软件根据调度算法从作业队列中选择合适的作业，并为其分配和释放计算结点。传统的作业调度和资源管理主要关注两点：降低作业的平均等待时间和提高整个系统的利用率。然而，由于没有足够的作业负载，以及作业调度和资源分配策略无法充分利用系统资源，常常会有空闲资源浪费系统能耗的情况。 针对以上问题，本课题分析了高性能并行计算系统负载与能耗的特点，并基于并行资源管理技术，设计了两类针对高性能并行计算系统的自适应功耗管理算法。两类功耗管理算法分别采用了限制资源分配和关闭空闲结点的方法。其中基于限制资源分配的算法根据系统利用率或作业平均slowdown的变化，自适应调整可用结点数目，并关闭非可用结点以节省系统能耗；关闭空闲结点的算法则根据结点的关闭间隔时间或请求和服务速率自适应调整结点的空闲时间阀值，并使空闲时间超出阀值的结点进入“睡眠”状态以节省系统能耗。实验使用来源于ParallelWorkloads Archive的负载对两类算法进行了测试，结果表明，两类算法均能在不违反性能限制的前提下，有效降低系统能耗。

摘要： In recent years, the direction of research to improve the performance of computing systems is fo- cused toward chip multiprocessor (CMP) designs with multiple cores and shared caches integrated on a single chip. To meet the increased demand for data, large on-chip caches are being embedded on the chip, shared between the multiple cores. The traditional bus-based interconnect architectures are non-scalable for large caches and cannot support the higher cache demand from multiple cores, which motivates the design of a network-on-chip (NoC) interconnect structure for shared non-uniform cache architecture (NUCA). The concept of NUCA caches proposes the division of the cache into multiple banks connected by a switched network that can support the simultaneous transport of multiple packets. The larger on-chip cache designs also result in higher power consumption which is a serious concern as fabrication scales down to the nano-technologies. This research focuses on the implementation of the location cache design in a NoC-based NUCA system with multiple cores, in combination with low-leakage L2 cache based on the gated-ground tech- nique. This system architecture helps to reduce the power of L2 cache along with the performance benefit of the on-chip network. The CMP cache system is implemented on a NoC-NUCA framework with a write-through coherency protocol. The features of CACTI and GEMS are extended to support a complete power and performance estimation of the system. A full-system simulation is performed on scientific and multimedia workloads to characterize the NoC-based system. An analysis of the power and performance of the proposed system is presented in comparison with the traditional cache structure in different configurations. The simulation results show that the NoC-based system with the location cache results in significantly saving the energy of the cache system over the traditional bus-based system in any configuration and also the NoC-based system without a l

关键词： 嵌入式处理器   多媒体应用   应用软件   设计框架   多处理器   多核结构   开发工具   多媒体处理  

摘要： 深入理解某个应用的数据访问方式,可以充分利用处理器潜在架构中的存储器和系统资源,从而开发可扩展的并行应用。

关键词： ARM7   双CPU   消息泵  

摘要： 针对通信系统中,DSP的控制功能往往不是非常强大,在应用中往往不得不把DSP作为目标系统专门负责复杂的运算,而采用另外使用一个主机(PC或是单片机)对整个系统的运行实行控制,提出了一种用共享内存方法来对双CPU间进行通信。实践证明共享内存通信满足了系统高运算量、高实时性、抗干扰性要求。

关键词： 多处理器   系统引导   单片机   DSP   接口   嵌入式平台  

摘要： 多处理器硬件平台模式在工业控制系统中应用广泛。而MCU+DSP的双处理器模式设计较为突出,利用DSP完成数字信号处理功能,MCU实现管理、通信、人机接口等异步系统控制功能。各处理器在功能上相互分工并通过数据传输完成预期任务,提高系统性能。给出了基于MCU+DSP嵌入式平台的主机接口与引导设计方案。

关键词： 多处理器   高级程序设计语言   编程   艺术   基础知识   NP完全问题   计算机系统   离散数学  

摘要： 这是一本论述多处理器编程理论与实践的综合巨著! 看这本书的读者应具备一定的离散数学基础知识，能够理解“大O”符号的含义，以及它在NP完全问题中所起的作用；熟悉计算机系统的基本组成部件，如处理器、线程、高速缓存等；为了能够理解书中的实例，还需要具备初步的Java知识（在使用这些高级程序设计语言之前，阐述了语言的相关功能特征）。书中提供两处附录以供读者参考：附录A包含程序设计语言的相关知识，附录B给出了多处理器体系结构的相关内容。

关键词： 移动机器人   无线传感器网络   分级控制系统  

摘要： 设计了一种适用于无线传感器网络环境的小型移动机器人,提出了一种基于多处理器的机器人分级控制系统,其中包括基于PIC18F8620单片机的主控制系统和基于Atmega8单片机的从控制系统,并详细阐述了控制系统的软硬件设计与实现。设计的机器人具有较好运动性能、定位性能、自主避障能力以及运行稳定性,不仅适用于无线传感器网络环境下机器人的研究,也适用于机器人竞赛等领域。