关键词： DDR   单芯片   可配置   数据总线   www   内存控制器   回声消除   ADC   可编程   队列   宽带处理   电池充电控制器   多处理器   功耗   位宽   功率放大器   功率放大电路   电源管理器   端口  

关键词： 监测接收机   ADSP-TS101   多处理器   PCB  

摘要： 摘 要 无线电通信技术的不断进步，极大地促进了无线电通信业务的发展，为了提 高频谱资源的有效利用，维护空中通道的畅通，无线电监测成为必要。近几年， 随着软件无线电技术的发展，监测设备的水平也取得了很大的进步。 本文涉及的宽带数字监测接收机采用的是 VXI 总线技术，并结合了最新的 软件无线电技术、DSP 技术，它的研究将可以满足我国无线电监测的实际需要。 随着 DSP 技术的飞速发展，DSP 处理器以他所具有的系统构成灵活、可编程、 运算速度快、数据处理和通信能力强以及适应面广的特点，使其广泛应用在通信、 航空航天、医疗仪器、工业控制等领域中。 本文作者主要研究监测接收机中多 DSP 处理模块的软硬件设计。宽带数字 监测接收机的中频处理数据量大、实时性高，对 DSP 芯片提出了很高的要求。 作者采用的是 AD 公司的高性能数字信号处理器 ADSP-TS101，ADSP-TS101 是 TigerSharc 系列 DSP 中的一款，具有工作频率高、强大的浮点运算能力、高速度 数据吞吐以及大容量的片内存储器的特点，非常适合在雷达、声纳、软件无线电 等领域全数字化处理中进行巨大的运算量和数据通信。本文提出了一种双 TigerSharc 结构的多处理器系统，第一片 ADSP-TS101 直接从 A/D 模块高速读取 数据，两片 TigerSharc 通过 Linkport 进行片间高速的数据传输，多处理器模块采 用一片 EPROM 对多片 ADSP-TS101 进行初始化程序加载。本文还对 PCB 布线 以及软件算法进行了初步的探讨，提出了一些有效的方法。

关键词： 多处理器   上位机   工业现场总线   小型控制系统   传输距离   测试数据   DIN   分布式   绝缘破坏   电子干扰   反电子措施  

摘要： This thesis involves modeling, design, Hardware Description Language (HDL) design capture, synthesis, implementation and HDL virtual prototype simulation validation of an interconnect network for a Hybrid Data/Command Driven Computer Architecture (HDCA) system. The HDCA is a single-chip shared memory multiprocessor architecture system. Various candidate processor-memory interconnect topologies that may meet the requirements of the HDCA system are studied and evaluated related to utilization within the HDCA system. It is determined that the Crossbar network topology best meets the HDCA system requirements and it is therefore used as the processor- memory interconnect network of the HDCA system. The design capture, synthesis, implementation and HDL simulation is done in VHDL using XILINX ISE 6.2.3i and ModelSim 5.7g CAD softwares. The design is validated by individually testing against some possible test cases and then integrated into the HDCA system and validated against two different applications. The inclusion of crossbar switch in the HDCA architecture involved major modifications to the HDCA system and some minor changes in the design of the switch. Virtual Prototype testing of the HDCA executing applications when utilizing crossbar interconnect revealed proper functioning of the interconnect and HDCA. Inclusion of the interconnect into the HDCA now allows it to implement "dynamic node level reconfigurability" and "multiple forking" functionality.

摘要： In this thesis we have devised a multi-processor based heuristic algorithm for the Multi-dimensional Multiple Choice Knapsack Problem (MMKP). MMKP is a variation of the classical 0-1 Knapsack Problem where there are multiple groups of items and more than one resonrce is required by each item. Admission control problem in an Adaptive Multimedia Server System can be mapped to MMKP. The problem is NP-hard which is not feasible for the real time admission control problem. So, heuristic solutions have been developed to solve the MMKP. Among all the heuristics, M-HEU developed by Akbar solves the MMKP achieving a reasonable percentage ofoptimality. This thesis presents an algorithm based on M-HEU using multiple processors. This algorithm runs in time O(T/p+ f(p ) where Tis the time required by the algorithm using single processor, p is the number of processors and j(p), a function of p, is the SYnchronizationoverhead. The worst case analysis of the algorithm and the computation of the optimal number of processors are also done.

摘要： Several trends in technology have important implications for embedded systems of the future. One trend is the increasing density and number of transistors that can be placed on a chip. This allows designers to fit more functionality into smaller devices, and to place multiple processing cores on a single chip. Another trend is the increasing emphasis on low power designs. A third trend is the appearance of bottlenecks in embedded system designs due to the limitations of long electrical interconnects, and increasing use of optical interconnects to overcome these bottlenecks. These trends lead to rapidly increasing complexity in the design process, and the necessity to develop tools that automate the process. This thesis will present techniques and algorithms for developing such tools. Automated techniques are especially important for multiprocessor designs. Programming such systems is difficult, and this is one reason why they are not as prevalent today. In this thesis we explore techniques for automating and optimizing the process of mapping applications onto system architectures containing multiple processors. We examine different processor interconnection methods and topologies, and the design implications of different levels of connectivity between the processors. Using optics, it is practical to construct processor interconnections having arbitrary topologies. This can offer advantages over regular interconnection topologies. However, existing scheduling techniques do not work in general for such arbitrarily connected systems. We present an algorithm that can be used to supplement existing scheduling techniques to enable their use with arbitrary interconnection patterns. We use our scheduling techniques to explore the larger problem of synthesizing an optimal interconnection network for a problem or group of problems. We examine the problem of optimizing synchronization costs in multiprocessor systems, and propose new architectures that reduce synchronization co

摘要： Fetch tokens is a method for increasing the performance of a single-thread process on a chip- multiprocessor (CMP) architecture. A fetch token, containing a target fetch point, is passed be- tween the processors to divide the dynamic instruction stream into regions. The regions are neither control nor data independent, but are simple to construct and analyze in hardware. Regions have an average size of 108 instructions of which 24% are independent of the previous region. This allows the execution of regions to overlap. Various heuristics are examined for determining when to pass the fetch token. I present methods for handling the data dependences between regions. To overcome significant challenges in dependence prediction, I use a frame-cache-based infrastructure. I have found that little information needs to be shared beyond the necessary data dependences. The additions to the microarchitecture are also few in number, small in size, and disjoint across the cores. The use of fetch tokens boosts performance by an average 11% on a four-wide dual-core CMP.

摘要： This thesis documents the implementation of a multiprocessor extension to a Sim- plescalar based full system simulator. The new multiprocessor simulator, called sim- smp, is able to run the Linux operating system, v2.4. xx, along with applications on top of itself. The architecture modeled by sim-smp is essentially MIPS32, due to the fact that the underlying Simplescalar simulator models a subset of the MIPS architecture. The mi- cro architecture modeled is a Symmetric Multiprocessor with shared level one caches, that maintain the MESI cache coherency protocol, and a unified level two cache. The simulator can be modified to collect a wide variety of statistics, and does by default collect statistics on caches, cache coherency traffic, bus activity etc. It can also be modified to model novel features that are to be evaluated. The sim-smp simulator is expected to be useful in research experiments where op- erating system activity causes effects that can not be neglected, alternatively in in ex- periments trying to characterize operating system effects or behavior. An interesting field of use is to characterize power consumption by incorporating a power consump- tion model into the simulator, which is interesting since power consumption is soon to become a bottle neck future embedded or mobile devices.

关键词： 视频编辑软件   多处理器  

关键词： 岩土力学   有限元方法   区域分解   共轭梯度法   PC机群  

摘要： 岩土工程规模大,加上岩土介质复杂的特性,使得当前有限元数值模拟在时间和精确度上很难达到工程要求.研究了在普通PC机群上实现的大规模并行有限元方法,以更好地发挥有限元在岩土工程中的应用.组建了Windows下PC机群并行系统.采用'分而治之'的并行策略实现有限元并行,并实现了存储局部化.采用基于区域分解预处理技术的并行共轭梯度法来实现方程组的求解.集成以上方法,用C++开发了并行有限元程序ParallelGeoFEM.对水布垭地下厂房进行了三维有限元并行模拟,得到了较好的加速比.结果表明,基于区域分解的并行有限元方法可以实现岩土工程大规模快速精细的模拟.