关键词:
誤差回授
雜訊移頻逐次逼近暫存式類比數位轉換器
單位增益緩衝器
低功耗
Error-feedback
Noise-shaping SAR ADC
Unity gain buffer
Low power
摘要:
In modern digital electronic devices, analog-to-digital converters (ADCs) play a crucial role. They find widespread use in numerous sectors, including communications, medical equipment, industrial control, instrumentation, and consumer electronics. With advancing technology and expanding application areas, there is an increasing demand for ADCs that are low power, high precision, and compact. Therefore, we aim to enhance ADCs focusing on low power consumption, high precision, and small *** paper presents a low-power third-order noise-shaping SAR ADC with an error feedback architecture. The circuit uses only one unity-gain buffer, effectively reduce overall power consumption and area cost. The employed unity-gain buffer is a complementary self-biased differential amplifier (CSDA), eliminating the need for additional common-mode feedback and bias circuits. Moreover, since the proposed architecture employs unity gain buffers and delay elements operating in a ping-pong manner to deliver the quantization error, there is no need to consider the matching degree between capacitors. Compare with traditional integrators, there will be better signal *** proposed ADC fabricated in TSMC’s 0.18-μm 1P6M CMOS process technology, with a chip core area of 0.417×0.669 mm2. It achieves an optimal SNDR of 85.17 dB at a sampling frequency of 2 MHz and a bandwidth of 20 kHz, corresponding to an ENOB of 13.86-bits. The power consumption of the proposed ADC at a 1.8-V supply voltage is 75.5 μW. The FoMs is 169.43 dB, and the FoMw is 126.53 fj/Conv..