关键词:
Muscular and ocular artifact removal
Electroencephalography
Denoising
Discrete wavelet transform
Independent component analysis
Brain Computer Interface (BCI)
摘要:
Background and objective: EEG is a non-invasive tool for neuro-developmental disorder diagnosis and treatment. However, EEG signal is mixed with other biological signals including Ocular and Muscular artifacts making it difficult to extract the diagnostic features. Therefore, the contaminated EEG channels are often discarded by the medical practitioners which may result in less accurate diagnosis. Many existing methods require reference electrodes, which will create discomfort to the patient/children and cause hindrance to the diagnosis of the neuro-developmental disorder and Brain Computer Interface in the pervasive environment. Therefore, it would be ideal if these artifacts can be removed real time on the hardware platform in an automated fashion and then the denoised EEG can be used for online diagnosis in a pervasive personalized healthcare environment without the need of any reference electrode. Methods: In this paper we propose a reliable, robust and automated methodology to solve the aforementioned problem. The proposed methodology is based on the Haar function based Wavelet decompositions with simple threshold based wavelet domain denoising and artifacts removal schemes. Subsequently hardware implementation results are also presented. 100 EEG data from Physionet, Klinik fur Epileptologie, Universitat Bonn, Germany, Caltech EEG databases and 7 EEG data from 3 subjects from University of Southampton, UK have been studied and nine exhaustive case studies comprising of real and simulated data have been formulated and tested. The proposed methodology is prototyped and validated using FPGA platform. Results: Like existing literature, the performance of the proposed methodology is also measured in terms of correlation, regression and R-square statistics and the respective values lie above 80%, 79% and 65% with the gain in hardware complexity of 64.28% and improvement in hardware delay of 53.58% compared to state-of-the art approaches. Hardware design based on the