摘要:
Over the last few decades, electronic circuits have more and more become a partof our lives, and their area of application expands continuously. As a result, thesecircuits are getting more and more complex through these areas of application. Theyare synthesized from hardware designs, which describe their functional and timingbehavior at a higher level of abstraction. Since safety-critical systems such as carsrely on these designs, it is essential to address the increasing complexity as it directlyimpacts the design's correctness. This dissertation investigates the increasing complexity of hardware designs byproposing and evaluating a hardware design synthesis flow that automaticallypropagates verification results from a formal specification to an implementation. A modelat the Electronic System Level (ESL) is automatically extracted from a specification atthe Formal Specification Level (FSL), and this model is synthesized into animplementation at the Register-Transfer Level (RTL). This automatic propagation contrasts withthe established hardware design flow, which relies on manual realizations at the ESLand RTL levels. Due to the missing propagation of verification results, these manualrealizations rely on the required test benches' quality. Consequently, similar verifi-cation tasks are repeated at different levels. The proposed synthesis flow combinesthe proof assistant Coq with the functional hardware description language CλaSH toachieve the automatic propagation of verification results. This combination avoidstest bench generation for the model and the implementation. Furthermore, the proposed flow allows the investigation of problems in the modelor the implementation already at the FSL level, e. g., arithmetic overflows for finiteinteger types. The established hardware design flow models infinite integer typesat the FSL level, which do not realize an overflow behavior. To specify finite integertypes at the FSL level, dependent types are used. Based on these types