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关键词： MOSFET   Stress   Logic gates   Threshold voltage   Temperature measurement   Semiconductor device measurement   Voltage measurement   Electron traps   Leakage currents   Filling   Deep-level transient spectroscopy (DLTS)   point defects   silicon-based MOSFET chips  

摘要： In this study, the electrical performance and evolution of point defects in chip-level Silicon-based MOSFET under transmission line pulse (TLP) stress were investigated. The experimental results show that the threshold voltage decreased by 9.8%, and the output saturation current increased by 5.9% after the stress. An intrinsic point defect with an energy level of 0.25 +/- 0.05 eV in Si-based MOSFET chips was observed by using deep-level transient spectroscopy (DLTS), which shifted to 0.37 +/- 0.05 eV after the stress. The increase of the trap energy level would reduce the holes at the Si/SiO2 interface, and herein the threshold voltage reduced. This work helps to further understand the evolution of point defects in Si-based MOSFET chips.

关键词： Switching loss   Semiconductor device modeling   Analytical models   Silicon carbide   Hysteresis   Numerical models   Switches   Analytical model   buck   dynamic   switching loss   threshold voltage instability   threshold voltage instability  

摘要： Accurate modeling of switching loss is critical for silicon carbide mosfets as well as power converters. However, previous "static" time-independent models did not consider the impact of gate oxide degradation on switching performance during long-term operation. This article proposes a "dynamic" time-dependent analytical model considering threshold voltage (V-TH) instability caused by gate oxide degradation to predict switching loss. The influence of V-TH instability on the turn-on and turn-off V-TH, as well as on switching loss during continuous operation is revealed first. Moreover, the problems suffered in the existing analytical model are investigated, and an improved switching loss model is presented. A measurement-based method to obtain the V-TH instability parameters for modeling is provided. Furthermore, a buck converter is built and operated under different conditions. Comparisons of switching waveforms and switching losses between experiments and the proposed model are given to validate the model. The results indicate that the proposed analytical model can effectively evaluate the switching loss, with an error within 7% under different continuous operating conditions. Finally, the universality of the proposed model for devices with different structures is verified, and a predication application of the model in operation is demonstrated.

关键词： MOSFET   Degradation   Logic gates   Silicon carbide   Stress   Insulated gate bipolar transistors   Switches   Degradation location   reliability   short-circuit (SC)   traps   traps  

摘要： Degradation of SiC power mosfets under repetitive short-circuit (SC) stress is significant to the reliability of the power systems. A deep level transient spectrum method together with split C-V method to split the trap characteristics of the SiC mosfets is proposed. The degradation details of different locations in SiC planar gate (PG) and trench gate (TG) mosfets are comprehensively studied in this article. Thus, a criterion is provided to guide the SC degradation from the aspect of traps. The main degradation of the channel region is the increase of border traps for PG mosfet and newly generated interface traps for TG mosfet. The interface traps domain the degradation in the JFET region for both devices. The degradations of gate oxide for both devices affect the channel and JFET regions especially in the first set of SC cycles. The degradation of body diode is mainly influenced by hole traps in PG mosfet, but by electron traps first then hole traps newly generated in TG mosfet. Finally, the degradation locations of PG and TG mosfets are effectively characterized. It is the first time to use the trap measurement method to separate the different degradation in every part of the devices in detail. The method proposed in this article can better reflect the failure mechanisms related to dynamics and evaluate the operation of devices effectively, which provides very useful guidance for the reliability design and utilization of SiC mosfets.

关键词： Noise   Logic gates   Couplings   Impedance   Silicon carbide   Integrated circuit modeling   MOSFET   Active gate driver (AGD)   common-source inductance   coupling noise   SiC mosfet  

摘要： The high switching speed of SiC mosfets is limited by the coupling noise in bridge-leg configurations. Conventional methods focus on the noise introduced by the gate-drain capacitance, which is suppressed by reducing the gate impedance with the active gate driver (AGD). However, when the common-source inductance (L-s) exists, noise spikes are not strictly increasing with gate impedance. The existing AGD parameter design methods have limited suppression effects. To fully utilize the noise suppression capability of AGD, this article constructs a noise mathematical model considering L-s, where the auxiliary branch is considered as RLC in series and the main factors affecting the coupling noise are all included. Based on the model, a parameter optimization algorithm is proposed. In detail, the noise spikes at different AGD parameters are calculated with a set of extracted switching characteristics. The proposed algorithm solves the AGD parameters with optimal noise suppression by using a designed cost function. The experimental results show that the variation trends of noise spikes at different AGD parameters can be accurately calculated. Compared with the conventional methods, the proposed algorithm suppresses noise spikes to optimal values. The optimization algorithm provides a guideline for the AGD parameter design.

关键词： Electronic circuits for signal processing   CMOS amplifier   Integrated circuits   MOSFET   g(m)/I-D methodology  

摘要： This paper presents the analysis and design of CMOS differential amplifiers using the first-order approach and sizing the transistors with the g(m)/I-D methodology. The design of four amplifiers using 130 nm CMOS technology is shown, and through spice simulation basic concepts of performance and compliance specifications are verified. The comparison of the performance of the designed amplifiers, in the synthesis of an active low-pass filter, is made to show that the fundamental performance parameters of each amplifier, affects the expected performance of the circuit under design, showing that the CMOS amplifier is not general purpose but that the application takes advantage of the characteristics of the amplifier or, alternatively, the amplifier is designed to meet the requirements of the application. Finally, while each architecture is sized using the same general performance specifications, it is also true that each has a specific and unique overall performance. These differences can be obtained and understood with spice simulation, since the resources of the simulation tool are used properly. All results obtained are at room temperature.

关键词： grid driver circuit control   silicon carbide MOSFET   double-pulse test circuit   voltage and current overshoot   LTspice  

摘要： Silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs), as a new material, have the advantages of low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency compared with silicon (Si)-based MOSFETs. Therefore, in many industrial applications, Si MOSFETs have been replaced by SiC MOSFETs. However, as the switching speed increases exponentially, some problems are amplified, the most serious of which is the overshoot of current and voltage. The increase in voltage and current slope caused by high switching speeds inevitably leads to overshoot, oscillations, and additional losses in the circuit. This paper focusses on the actual performance of the optimised switching strategy (OSS) in circuit testing and combines the existing simulation results to verify the practicability of OSS. In this paper, the optimised switching strategy is introduced first, and then, the LTspice model of SiC MOSFET is established in detail and verifies the feasibility of the OSS through half-bridge circuit simulation. Finally, the test platform is built using a programmable gate drive module (2ASC-12A1HP). Through a 400 V/30 A double-pulse test, the practicality of the OSS is verified. The experiments show that the OSS can greatly improve the switching performance of SiC MOSFETs.

关键词： Silicon carbide   MOSFET   Logic gates   Multichip modules   Voltage control   Oscillators   Switches   Gate charge injection (GCI)   silicon carbide (SiC) MOSFET   snubber circuit   switching oscillation   switching overvoltage  

摘要： Due to the inherent parasitic inductance and high switching speed, the SiC mosfet generally experience significant overvoltage and oscillation, reducing the voltage margin and causing substantial electromagnetic interference. To mitigate these challenges, a novel auxiliary circuit using the gate charge injection (GCI) concept is proposed in this article. The GCI circuit, assembled across the drain-gate of the SiC mosfet, injects charges into the gate during the overvoltage stage of the turn-off process, effectively reducing overvoltage and oscillation without affecting the turn-off speed. The mechanism of the proposed GCI circuit is meticulously analyzed interval by interval based on the cell structure of the SiC mosfet, and its parameters are designed and validated through the circuit simulation. Additionally, the proposed GCI circuit, comprising Si-RC and PiN diode die, is integrated into the SiC power module and assessed by the double pulse test and power cycling test. Experimental results show a 70% reduction in the transient overvoltage at 600 V/30 A and complete the oscillation elimination, with only a 3.4% increase in the switching loss. The GCI circuit does not affect the turn-on process, making it an effective and cost-competitive solution for suppressing the overvoltage and oscillation in the SiC power module.

关键词： Transistors   Couplings   MOSFET   Semiconductor device modeling   Logic gates   Capacitance   Electric potential   Timing   Silicon   Fluctuations   Back end of line (BEOL)   capacitive coupling   oxide semiconductor   2 transistor gain cell (2TGC)  

摘要： In this article, the impact of capacitivecoupling in the oxide-channel-based 2 transistor gaincell (2TGC) is evaluated. The study is performed using anexperimentally calibrated TCAD model of W-doped In(2)O(3)transistor (IWO MOSFET) in the mixed mode simulation.A write "0," read "0," write "1," read "1" (W0R0W1R1) oper-ation is performed and the storage node (SN) potential ismonitored. The SN is capacitively coupled to write and readwordlines (WWL and RWL), which temporarily lowers theSN potential after writing and during a read operation. Foran improperly designed 2TGC, capacitive coupling leads toa disturbed read for bit "0," and reduced sense margin forbit "1." To mitigate this problem,V-TH engineering, appropri-ate choice ofV(HOLD), and sizing of individual transistors ishelpful. To substantially suppress the capacitive coupling,a split gate (SpG) structure design for IWO MOSFET is pro-posed, which allows for a sizing-independent 2TGC designwith an undisturbed read and a higher sense margin thanthe traditional design.

关键词： MOSFET   Logic gates   Silicon carbide   Semiconductor device modeling   Trajectory   Degradation   Junctions   Device model   dynamic behavior   short circuit (SC)   SiC MOSFET  

摘要： A compact model could be an efficient tool and general solution to accurately predict the short-circuit (SC) dynamics of the SiC mosfet. In this article, an SC test setup is constructed to collect the model data, where no physical information of the SiC mosfet is required. The SC trajectory in the safety state and failure state is measured, and then the cumulative degradation of the gate oxide and effect of temperature rise during each SC dynamic are included in the proposed SPICE model. Meanwhile, the SC dynamics are modeled in detail under gate-oxide damage and thermal runaway failure modes. So, the SC trajectory and failure moment of the SiC mosfet could be correctly predicted by the application of the proposed model. The proposed model is verified in the SC test and a three-level converter, respectively. The good accuracy and convergence of the proposed model are confirmed by comparing with the experimental results. The generality of the model is also validated in different software and devices. The proposed model would be a favorable tool for the high robust design of the SiC mosfet-based converters.

关键词： Oscillators   Logic gates   Inductance   Gallium nitride   Silicon carbide   Stability criteria   MOSFET   False triggering oscillation   gallium nitride (GaN) devices   parallel operation  

摘要： Gallium nitride (GaN) devices are being used more and more due to the advantages of fast switching speed and low on-state resistance. However, these advantages may also cause severe switching oscillations, such as false triggering oscillation. This oscillation can significantly impact system performance by causing overshoot, severe electromagnetic interference, and even device damage. Compared to a single device, paralleled GaN devices are suitable for applications requiring higher current and power, that will introduce a more complex parasitic parameter network, thus making it more susceptible to false triggering oscillation. However, the mechanism responsible for the occurrence of false triggering oscillation in parallel-connected GaN devices remains inadequately investigated, especially under asymmetry. This article presents a comprehensive analysis of false triggering oscillation in parallel-connected GaN devices by integrating the operational theory and stability criteria of paralleled devices. First, the oscillation mechanism and behavior of paralleled GaN devices under asymmetry are analyzed. Then, an equivalent circuit model with considering parasitic parameters is developed to accurately represent false triggering oscillation. Furthermore, the impact of parallel circuit parameters on stability is investigated. Finally, experimental validation confirms the accuracy of proposed analysis and provides design recommendations for reducing false triggering oscillation in paralleled GaN devices.