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关键词： 4H-SiC   Double trench   MOSFET   Integrated Schottky barrier diode   Inverted-T groove  

摘要： In this letter, we propose an improved 4H-SiC double trench MOSFET with Inverted-T groove and integrated Schottky barrier diode (ITSBD-MOS). The device features an Inverted-T groove beneath the gate electrode and the integrated SBD locates on the bottom of source trench. Numerical simulations have been completed to study the proposed device. The maximum electric field in gate oxide of ITSBD-MOS is suppressed to below 3 MV/cm, while the turn-on voltage in reverse conduction state is lowered to 1.23 V. Besides, due to the introduction of Inverted-T groove, the gate-to-drain charge of the ITSBD-MOS is significantly reduced while the shortcircuit capability is obviously improved. The calculated high-frequency figure of merit (HFFOM = R on,sp x Q gd ) of ITSBD-MOS is tremendously decreased compared with that of DT-MOS, which suggests that ITSBD-MOS is a promising candidate for external-diode free power electronics applications and high-frequency operations.

关键词： Threshold Voltage   Extraction Method   Cryogenic   DIBL  

摘要： It is well known that different threshold voltage (Vth) extraction methods exhibit inconsistencies with respect to different drain voltage (Vd). This inconsistency becomes disruptive when temperature is considered for cryogenic applications such as quantum computing. This investigation examines various V th extraction methods from room down to cryogenic temperatures, with a particular emphasis on how different Vd values combined with extraction methods behave as temperature decreases. For the first time, we find that the square root Id method maintains consistency regardless of V d , from 300 K all the way down to 10 K is identified. This provides a good insight into how the Drain-Induced Barrier Lowering (DIBL) effect changes with temperature, and positions the square root Id method as a reliable tool for V th extraction in cryogenic temperature.

关键词： Junctionless MOSFET   Tubular Channel   Interface trapped charges   Gate-engineering   Temperature induced variations   Surrounding gate  

摘要： Current research presents the mathematical modeling highlighting the interface trap charge degraded characteristics of Surrounding Gate-Engineered Tubular Channel Junctionless MOSFET including temperature variation. Salient device features such as drain current, Ion/Ioff ratio, transconductance, off-current temperature sensitivity, threshold voltage have been explored to investigate the temperature influences comparing the damaged and undamaged configuration of the device. Extent of subthreshold swing variations under thermal influence has been analyzed. Impact of channel length scaling, channel thickness and oxide-thickness variation on device features have also been reported in this research. Analytical outputs have been corroborated using simulation outputs from Silvaco Atlas 3D.

关键词： Latches   Logic   Transistors   Testing   Defect detection   Clocks   MOSFET   Simulation   Production   Low voltage   Design-for-test (DFT)   hardened latch design   process   voltage   and temperature (PVT) variation   production defect   single-event-upset (SEU)  

摘要： Soft errors have been a severe threat to the reliability of modern integrated circuits (ICs), making hardened latch designs indispensable for masking soft errors with redundancy. However, the added redundancy also masks production defects as soft errors;this makes it hard to detect defects in hardened latches, thus significantly reducing their reliability. Our previous work proposed the scan-test-aware hardened latch (STAHL) design, the first for addressing the issue of low defect detectability of hardened latch designs. However, STAHL still suffers from two problems: 1) it is not self-resilient to soft errors and 2) a STAHL-based scan design requires one additional control signal. This article proposes a high defect detectable and single-event-upset (SEU)-resilient robust (HIDER) latch to address the issues of the low defect detectability of existing hardened latches and the STAHLs lack of SEU-resilient capability. Two scan designs HIDER-based scan-cell-S (HIDER-SC-S) and HIDER-based scan-cell-F (HIDER-SC-F), as well as two corresponding test procedures, are proposed to fully test HIDER latch with only one control signal. Simulation results show that the HIDER latch achieves the highest defect coverage (DC) in both single latch cell detection and scan tests among all existing hardened latch designs. In addition, the HIDER latch has much lower power and a smaller delay than STAHL.

关键词： Electronic water pump   FLUENT   MOSFET   Void rates   Thermal resistance  

摘要： In automotive electronic water pumps, MOSFET is used as power conversion devices to drive water pump motors, however, the high temperature of the engine will cause the electronic water pump MOSFET to overheat and fail. In order to effectively reduce the overheating failure of MOSFET, a thermal simulation model of printed circuit board MOSFET for automotive electronic water pump controllers was established using FLUENT software. The temperature rise characteristics of MOSFET with different void rates under single and multi-void SMT states were analyzed. The analysis results indicate that the thermal resistance of MOSFET in printed circuit boards increases with the increase of void fraction, and the simulation results are verified through experiments, which are consistent with the simulation results. At the same time, when the void ratio is greater than 10 %, the heat dissipation effect of a single void is more pronounced than that of a void. The thermal analysis of printed circuit board MOSFET provides support for effectively controlling MOSFET temperature rise and reducing MOSFET thermal failure.

关键词： Automatic parameter extraction method   nonlinear capacitance   physical model   SiC MOSFET   Automatic parameter extraction method   nonlinear capacitance   physical model   SiC MOSFET  

摘要： The terminal capacitances of SiC power devices can significantly influence their switching characteristics. Consequently, it is crucial to accurately characterize the nonlinear characteristics of terminal capacitances. This article provides a unified PSPICE modeling approach for SiC MOSFET that is based on the physical characteristics of nonlinear terminal capacitance. The model takes into account the depletion region variation and structure of terminal capacitance during the operation of planar gate SiC MOSFET. The terminal capacitances are calculated by analyzing their dual dependence on the gate-to-source voltage V-gs and drain-to-source voltage V-ds. More importantly, an automatic parameter extraction method is proposed for the model to extract the unknown parameters that are in accordance with the experimental characteristics. The proposed modeling method precisely depicts the relationship between the three terminal capacitances and the two independent variables, i.e., V-gs and V-ds, thereby circumventing the challenge of acquiring CV(C - V-gs and C- V-ds) characteristics curves. To confirm the proposed model's accuracy and generalizability for planar-gate SiC MOSFET, investigations are conducted using two distinct planar-gate SiC MOSFET devices: the SiC MOSFET C2M0080120D (1200 V/36 A) and the SCT30N120 (1200 V/45 A). The measurements from the double-pulse experiments are in good accordance with the results by our model. In addition, the convergence capability of our proposed model is confirmed through PSPICE simulation of a BUCK converter.

关键词： Voltage   MOSFET   Silicon carbide   Transformers   High-voltage techniques   Modulation   Capacitors   Asymmetric bipolar pulse   high repetition rate   solid state pulsed power modulator (PPM)  

摘要： This article proposes a solid-state pulsed power modulator (PPM) with asymmetric bipolar pulses and high repetition rates for semiconductor manufacturing processes. Since the proposed PPM is based on high voltage solid-state switches (HVSSes) consisting of series connected silicon carbide (SiC) metal-oxide silicon field effect transistors (MOSFETs), it is simple to obtain variable asymmetric bipolar pulses as well as unipolar pulses. To solve the voltage unbalance problem, which is a critical challenge when the SiC MOSFETs are connected in series, a simple voltage balancing circuit is proposed. This balancing circuit shows superior features such as low loss and high reliability because it is composed of only passive components such as transformers and capacitors. In addition, the proposed PPM can achieve the high repetition rate since the soft switching of all SiC MOSFETs can be accomplished by the balancing transformer. Furthermore, the soft switching characteristic and the low loss of balancing circuit can contribute to the miniaturization of PPM by reducing the sizes of components and cooling systems. The design and implementation of 5 kV PPM with high repetition rate of 500 kHz are presented. Experiment results from the developed PPM are shown to verify the proposed works.

关键词： Weak energy wireless transmission   Ultrathin insulator on silicon   Back bias regulated threshold voltage   Rectification efficiency  

摘要： This paper presents and optimizes for the first time the design of UTB SOI MOSFET and its connection method for 2.45 GHz weak energy density harvesting, and optimizes the device structure parameters by Sentaurus TCAD software, so that the device exhibits the desired characteristics of high forward bias current and low reverse leakage current. The new connection method utilizes the device's back bias regulated threshold voltage to enable the device's dual gates to simultaneously control the channel current, resulting in a highly efficient RF-DC rectifier at a modest energy density of 2.45 *** Sentaurus Mixmode circuit mixing simulation module shows that in a half-wave rectifier circuit with loads of 0.1 pF and 20 k Omega, the single-tube energy conversion efficiencies of the new device reach 9.95 % and 19.27 % at input energies of -16 and -10 dBm, respectively, which are 2.73 and 2.48 times that of a silicon-based MOSFET under the same conditions.

关键词： Transconductance  

摘要： This research article presents a simulation study on a dielectric pocket engineered dual metal nanowire ferroelectric (DPE-DM-NW-Fe FET) MOSFET. The aim is to mitigate the Gate-Induced Drain Leakage (GIDL) effect in the off-state condition and improve the subthreshold swing. GIDL is a type of SCE which is detrimental for the device as continuous gate leakage current. Severely hamper the performance of the device particularly in analog applications. To prevent this a novel structure is proposed in which two dielectric pockets are introduced adjacent to the source and drain to reduce the SCEs. GIDL occurs even when the gate voltage is nearly zero, but it becomes significant when the gate region is at a lower bias and the drain region is at a higher bias. The introduced dielectric pockets act as diffusion stoppers, forming insulating barriers to prevent off-state current. Simulation studies were conducted to analyze off-state GIDL currents for different channel lengths (30 nm, 40 nm, and 50 nm). Various parameters such as electric field, electron concentration, electron velocity, and surface potential have been simulated and compared with a Single Metal Gate (SMG) cylindrical MOSFET. Critical performance parameters including drain current, transconductance (gm), output conductance (gd), input capacitance (CGG), cutoff frequency (fT), gain transconductance frequency product (GTFP), gain frequency product (GFP), maximum transfer power gain (MTPG), unilateral power gain (UPG), and early voltage (Vea) have been calculated. Additionally, the noise performances of the DPE-DM-NW-Fe FET have been examined, and its implementation as a CMOS inverter have been explored for determining noise margins. The lower noise margin makes the device suitable for high-frequency applications. The simulations have been conducted using the ATLAS-3D simulator.

关键词： Predictive models   Wires   Bonding   Semiconductor device modeling   Schottky diodes   Packaging   Mathematical models   Junctions   Silicon carbide   MOSFET   Life testing   lifetime prediction   power semiconductor devices   statistics  

摘要： Power semiconductor devices are the core components of power electronic systems and the most fragile part. Power cycling tests (PCTs) and lifetime prediction models are the two main means to obtain the lifetime of semiconductor power devices. This article collected PCT data on silicon (Si) and Si carbide (SiC) semiconductor devices from 2010 to the present. The impacts of different packaging technologies, testing methods, product types, manufacturers, etc. on the lifetime of semiconductor devices are discussed and analyzed. In addition, semiconductor power devices were clarified into three types, normal modules with aluminum (Al) bonding wires and solders, single-improved modules with solder improvement or bonding wire improvement, and double-improved modules with both solder improvement and bonding wire improvement. The lifetime model for each type was fit. Results showed that the fit lifetime prediction formula had high accuracy, with an average multiple of 1.4-2.8 times for the predicted lifetime with the experimental data.