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关键词： Inductance   Multichip modules   Silicon carbide   Copper   Conductors   MOSFET   Cooling   Double-sided cooling packages   low parasitic inductance   silicon carbide  

摘要： Higher switching speed requires power module package to have lower parasitic inductance. This article summarized three methods to realize low parasitic inductance. Based on these methods, this article proposed a novel double-sided cooling power module structure, which places the spacer under the bare die and utilizes the copper clips to realize the electrical connection between different copper layers. The proposed structure realized an interleaved power loop by utilizing copper clips and split dc terminals. Compared to the double-loop double-sided cooling power module structure, the parasitic inductance of the proposed structure can be decreased by more than 50% and that is only 1.3 nH. Besides, the dynamic current sharing properties and thermal performance of the proposed structure are also analyzed. Based on the proposed module, a module with three SiC mosfets in parallel is designed, fabricated, and tested to verify its low parasitic inductance performance. The proposed power module will contribute to achieving high power density applications.

关键词： Logic gates   Semiconductor device measurement   Fluctuations   Current measurement   Noise   Neuromorphic engineering   Tunneling   Flash memory   MOSFET   synaptic device  

摘要： A novel method of analyzing the dynamic read variation (equivalent gate bias deviation delta(V-G) over a wide gate-voltage range of devices is proposed and applied to CMOS-compatible TFT-type synaptic devices with poly-Si channel. Since the proposed method of current sampling in a time domain or DC sweep shows a similar trend of delta(V-G) for any FET-like devices, read variation can be estimated simply with greatly reduced measurement time. In addition, the proposed method can be utilized to analyze the reliability characteristics of FET-like devices, which is a promising solution to the current need for innovative analysis methods required as the devices become smaller. Considering dynamic variations of the fabricated synaptic device, the quantized VGG9 network for CIFAR-10 image classification simulation shows a < 0.1% accuracy drop compared to an ideal network without variation. Due to its simplicity and usability, the proposed method can be used for both commercial flash memory cells and neuromorphic computing devices.

关键词： Logic gates   Silicon carbide   MOSFET   Circuit faults   Switches   Protection   Resistance   Gate current   short-circuit protection (SCP)   silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET)  

摘要： Fast and reliable protection against short-circuit (SC) faults is critically important for the reliable operation of power devices. In this letter, an ultrafast and universal short-circuit protection (SCP) method is proposed for silicon carbide metal-oxide-semiconductor field-effect transistors based on gate current detection. This method exploits the characteristic of the gate current to become negative during SC faults and constant positive during normal operation. The proposed gate current detection approach swiftly identifies faults during the SC process, ensuring rapid response time. In addition, this method boasts broad applicability, being effective for both hard switching faults (HSFs) and faults under loads (FULs), and no extra auxiliary design is required for the three-pin device. The efficacy of the proposed SCP technique is validated through the testing of the SCP circuit. Experimental results demonstrate that the proposed circuit is applicable to both HSFs and FULs, with response delays of 69 ns for HSFs and 50 ns for FULs, and total protection trigger time of 383 ns for HSFs and 352 ns for FULs.

关键词： Silicon carbide   Silicon   JFETs   Topology   Inrush current   Motors   MOSFET   motor start   power modules   semiconductor device packaging   SiC FET   solid-state circuit breaker   solid-state contactor   thyristors   wide-band-gap devices  

摘要： Solid-state contactors are an emerging solution in various load-switching applications such as direct-on-line starting of induction motors. The design challenge of solid-state motor contactors (SSMCs) comes from a high motor-starting inrush current defined in IEC 60947-4-2 standard. To overcome the limitation of conventional SSMC solutions using silicon thyristors (Si SCRs), a novel "ThyFET" topology is proposed to combine the high inrush tolerance of Si SCRs with the efficient nominal conduction of silicon carbide junction field-effect transistors. In this article, the ThyFET circuit is first analyzed with current commutation principles and switching waveform simulations. Next, the packaging design of a 1.2 kV, 12 A, three-phase, bidirectional ThyFET module is presented, which adopts a three-dimensional structure to minimize the module footprint meanwhile handling the thermal stress. The ThyFET SSMC prototype is then assembled and evaluated with IEC-standardized benchtop tests and direct-on-line motor-starting tests with a 480 V, 5.6 kW induction motor load. The test results have validated the light-load efficiency boost and the distortion reduction in the ThyFET SSMC as compared to commercial SSMC products. Finally, the outstanding inrush handling capability of the ThyFET circuit is highlighted by comparing to other hybrid Si/SiC switches in the literature.

关键词： Silicon carbide   power MOSFET   specific on-resistance   cell pitch   source contact  

摘要： Reducing the on-resistance of SiC MOSFETs is crucial for lowering power losses and is a key aspect of MOSFET design. This letter proposes a recessed source contact (RSC) process, which utilizes the side contacts of the recessed contact structure to increase the effective contact area after narrowing the contact window width. This technology can reduce cell pitch as well as specific on-resistance without sacrificing other resistance components. In our demonstration of 1.7 kV VDMOSFETs, reducing the cell pitch from 6.2 mu m to 5.0 mu m by shrinking the contact width with the assistance of the RSC structure decreases the specific on-resistance by 12.6%. Conversely, without employing the RSC structure, the specific on-resistance increases by 5%. Furthermore, the RSC process allows for continuous P-well contact. Since the P+ contact is embedded under the N+ source, the depth and width of the P+ layer are not constrained by the N+ source layer.

关键词： Logic gates   Transistors   Threshold voltage   MOSFET   Gallium nitride   Current density   Dry etching   GaN   vertical trench gate transistors   MOSFETs  

摘要： Despite successfully demonstrating GaN trench gate vertical transistors for power electronics, the devices possess inconsistent electrical properties that depend strongly on the process conditions. This work compares the vertical transistors' threshold voltages and current densities with sidewalls treated by either H3PO4 or TMAH (tetramethylammonium hydroxide). With the H3PO4 sidewall post-etching treatment, the device's threshold voltage can be restored to a higher value of 7.2 V by removing donor-type defects incurred during sidewall dry etching in the p-GaN region. In comparison, the threshold voltage of the TMAH-treated device is 0.1 V. Surface treatment also affects the current density because it changes the effective gate length and sidewall orientation. A flatter sidewall profile after H3PO4 treatment results in a larger effective gate length and smaller carrier mobility when transporting in the semipolar GaN crystalline plane. The current density of the H3PO4-treated device is smaller than that treated by TMAH.

关键词： MOSFET   Silicon carbide   Switches   Gate drivers   Logic gates   Voltage control   Control systems   Active gate driver (AGD)   silicon carbide metal-oxide-semiconductor field-effect transistor (SiC mosfet)   slew rate control   switching loss   voltage spike  

摘要： Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC mosfets) are widely used in high-performance power converters due to their superior switching characteristic. The increase of the switching speed improves the efficiency of the system, whereas this also brings undesirable problems, such as voltage spikes and crosstalks. Most existing gate driver methods cannot flexibly regulate device switching speeds to match system requirements. To facilitate the devices operating in the desired state, this article proposes a cost-efficient active gate driver (AGD) for seamless slew rate control of SiC mosfets. By implementing two simple tunable current sources as the power supply, the proposed AGD regulates the turn-on/off speed of SiC mosfets independently. The operation principle of the proposed AGD is presented, which enables a practical parameter design method. The effectiveness of the AGD is experimentally validated, which can provide a wide slew rate range of 2.08 to 20 V/ns. Besides, compared to other AGDs with similar features, this cost-effective scheme can save almost 90% of hardware costs. In addition, due to its simple hardware composition, this scheme has the possibility of being integrated into a single chip, which has promising industrial application prospects.

关键词： Memristors   Voltage   MOSFET   Logic functions   Libraries   Databases   Reviews   Data-driven inductive learning (IL)   enumeration   logic cells   memristors  

摘要： The objective of our research is to create efficient methods and tools for the quick and thorough assessment of emerging digital circuit devices, facilitating the adoption of promising ones. In this work, we develop methods and tools for hybrid technology that combines memristors with MOS transistors and demonstrates their effectiveness. Although several types of memristor-transistor logic have been proposed, 15 years of research has created a small set of logic cells. We propose a systematic method for generating new and efficient memristor-transistor single-phase combinational logic cells. At the core of our approach is a cell enumerator, which enables us to explore a wide range of cell designs, including nonintuitive ones, and a data-driven inductive learning method, which identifies new properties of such cells and scales up our explorations. In conjunction with other completely new tools, these create a comprehensive and definitive library of logic cells. Our new cells provide significant improvements or significantly distinct Pareto-optimal alternatives for the few logic functions for which prior research has created cells. Importantly, our methods enable us to discover a previously unknown synergistic operation between memristors and transistors that occurs for specific cell topologies. We harness this synergy to develop a method for adding memristors to low-area pass-transistor circuits such that they produce strong output voltages and low power, including for patterns that cause ratioed operation. We have also developed a new memristor-transistor logic family, namely controlled-AND (cAND)/controlled-OR (cOR), which includes many of the best cells. We have also developed a constructive method for designing such cells.

关键词： Noise   Fluctuations   Scattering   Resistance   MOSFET   Logic gates   Voltage fluctuations   Correlated carrier number and mobility fluctuations (CNF/CMF)   low-frequency noise   Y-function  

摘要： In this article, it is proven that in the framework of carrier number fluctuation mechanism, the input referred voltage noise is equal to the flat-band voltage noise only if the access resistances give a negligible contribution to the total device resistance. The expression of the correlated carrier number and mobility fluctuations (CNF/CMF) noise is revisited, and compact analytical equations are proposed. It is demonstrated that if the degradation of the intrinsic mobility in strong inversion is not too significant, considering a constant intrinsic Coulomb scattering coefficient or a constant intrinsic effective Coulomb scattering coefficient leads to similar extracted noise parameters. It is also proven that a constant extrinsic effective Coulomb scattering coefficient is physically incorrect if the access resistances impact cannot be neglected in the total device resistance.

关键词： SiC MOSFET   Device modeling   Temperature scaling   Parameter extraction   Validation  

摘要： In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.