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关键词： Integrated circuit modeling   Semiconductor device modeling   Analytical models   MOSFET   Circuits   Transistors   Power demand   MOSFET non-linearity model   differential pair non-linearity   charge-based   EKV model   drain voltage induced non-linearity   OTA non-linearity   amplifier non-linearity  

摘要： Energy efficiency is of utmost importance in modern applications. Power consumption optimisation could be improved by a comprehensive analytical modeling of the characteristics of critical blocks in a system. Dynamic range (DR) has a strong effect on the power consumption of analog circuits, and is determined by circuit non-linearity and noise level. Noise is well modelled even in deep sub-micron technologies, yet there is a lack of analysis and modeling of the non-linearity. An analytical MOSFET differential pair non-linearity model is presented in this work. The proposed model is universal to a wide range of technologies from long to ultra-deep sub-micron devices, and is valid for all operating regions as it is based on the EKV MOSFET model. Furthermore, a model including drain-voltage-induced non-linearity is also developed, and a concise 3 dB input intercept point (IIP3) formula incorporating the drain induced non-linearity in terms of the voltage gain is presented. The proposed models are validated with DC and AC simulations and measurements.

关键词： kink effect   modified conventional current-voltage characteristic curves   bremsstrahlung   phonon  

摘要： FinFET transistors with fin channel lengths of 160 nm and 2000 nm and a planar MOSFET transistor with channel lengths of 180 nm and 90 nm are presented with characteristic curves at various Gate biases. A finalized algorithm with kink effects was effectively responsible for addressing the field effect transistors. The algorithm included the modified conventional current-voltage formula and a nonlinear heat-associated kink solution which was simplified as a Gaussian form. Three parameters in the modified model included kN (which was related with channel width, channel length, and gate oxide capacitor, and was proportional to the mobility of carriers), Vth (threshold voltage), and lambda (the inverse of early voltage). Those parameters were determined to minimize the discrepancies between the measured data and the fitting values, but left kinks located at around (VGS-Vth), which were deliberately eliminated by the Gaussian form because of the agitation of thermal kink effects. The whole fitting was made to be as close as possible to the as-measured IDS-VDS. In the meantime, those determined parameters were physically meaningful after the analysis had been performed.

关键词： Logic gates   Silicon carbide   Resistance   MOSFET   Degradation   Temperature measurement   JFETs   Gate-oxide degradation   junction temperature   monitoring   residual resistance   silicon carbide (sic) mosfets   thermo-sensitive electrical parameter (TSEP)  

摘要： Estimating the junction temperature of silicon carbide (SiC) mosfets plays a crucial role in enhancing their reliability in practical applications. Thermo-sensitive electrical parameters (TSEP) are commonly employed. However, the accuracy of junction temperature estimation using these TSEPs is usually reduced by gate degradation, as their correlation with temperature varies with the extent of gate degradation. To solve this problem, this article proposes an online junction temperature estimation approach that is independent of gate degradation. This method is based on residual resistance, which is the on-state resistance excluding channel resistance. First, the composition and temperature dependence of residual resistance are analyzed. The residual resistance exhibits a significant temperature dependence, which is extracted based on the SiC mosfet model and double-pulse test. The reason by which it is unaffected by gate degradation is also analyzed. Next, a method is proposed to effectively eliminate the impact of gate degradation on online residual resistance extraction. Third, the junction temperature estimating strategy based on residual resistance is proposed, and the corresponding gate drive circuit is developed. Finally, practical implementation and estimation errors are presented for both unaged and aged situations, using one planar and one trench SiC mosfet. Experimental results confirm the proposed approach's feasibility and accuracy.

关键词： 高频放大器   微波放大器  

ISBN: (纸本)9787121489273

摘要： 本书从工程设计要求出发，以多家公司的射频与微波功率放大器为基础，介绍了射频与微波功率放大器及其参数，以及射频与微波晶体管功率放大器应用电路、单片射频与微波功率放大器应用电路、射频与微波功率检测/控制电路和电源电路、射频与微波电路PCB设计、射频与微波电路热设计等电路设计和制作中的方法、技巧和应该注意的问题。

关键词： MOSFET   Negative feedback   Temperature distribution   Transistors   Thermal stability   Modulation   Microelectronics   Safe-operation-area   linear mode   self-adjusting negative feedback   varied resistance of patterned source  

摘要： VRS-SGT (Varied Resistance of Source Split Gate Trench MOSFETs) with self-adjusting negative feedback to balance the electrical and temperature characteristics, employing the varied resistance of patterned source is firstly developed in this letter to improve safe operating area (SOA) for automotive power devices used in linear mode. When operating in the linear mode, the max I-d of VRS-SGT raises to 20 A in condition of V-d = V-g = 10 V and PT = 10 ms, increased by 48% compared with Conventional-SGT (C-SGT) due to lower ZTC and weaker positive current-temperature feedback. In addition, the low doping N-region for source resistance helps the VRS-SGT set up the self-ballast negative feedback mechanism to increase the source potential ( V-s ), which can further suppress the trigger of parasitic NPN while slowing down the startup of MOSFETs. Varied R-s in N-region can adjust the current distribution within the chip so that the temperature tends to be more uniform when operating in linear mode. In addition, the Rds-on of VRS-SGT increases by only 3%, achieving a good trade-off between SOA and Rds-on.

关键词： Video recording   Capacitors   Topology   MOSFET   Switches   Power system measurements   Density measurement   Conversion-ratio modulation (CRM)   dc-dc converter   Internet of Things   reconfigurable converter   switched-capacitor converter   voltage conversion ratio (VCR)  

摘要： This article presents a fully integrated step-down switched-capacitor (SC) converter with nine voltage conversion ratios (VCRs) that regulates an output load voltage ( $V_{\text{OUT}}$ ) of 0.1-3.67 V with an input voltage of 2.5-5 V. The proposed converter employs 5-V metal-insulator-metal capacitors and 1.8-V native MOSFET capacitors to achieve both power density and conversion efficiency that are suitable for the Internet-of-Things (IoT) applications. In addition, the power stage is operated by the proposed overlapped-conversion-ratio modulation (OCRM), which prevents the severe closed-loop efficiency loss caused by conventional VCR control schemes. Thus, the proposed converter regulates $V_{\text{OUT}}$ through digitally controlled 15 nine-ratio SC cells, enabling the frequency-scalable power conversion operation. With a 180-nm CMOS process, the proposed converter achieves 87 $\%$ peak efficiency and the maximum output power of 421 mW.

关键词： Silicon   Analytical models   Logic gates   Capacitance   Switches   Silicon carbide   Semiconductor device modeling   Analytical model   double pulse test (DPT)   loss   MOSFET   Schottky diode   SiC   silicon superjunction   switching transient  

摘要： With high reliability and good cost-performance ratio, silicon superjunction MOSFETS (Si SJMOS) and SiC SBD pair is often preferred in commercial single-phase power factor correction applications. Switching dynamics of Si SJMOS are different compared to 650 V wide bandgap devices due to differences in device characteristics. This article presents an improved analytical model to study the switching dynamics of Si SJMOS and SiC SBD pair. Unlike the existing literature on high-voltage Si MOSFETS, this article considers the nonlinearities in channel current and internal capacitances of Si SJMOS, the nonlinear reverse-biased capacitance of SiC SBD, along with parasitic gate-drain capacitance arising due to PCB layout. As a result, the proposed analytical model presents a significant improvement over the existing models of high-voltage Si MOSFET in predicting switching loss, time, (dv/dt), (di/dt), etc. Experimental and simulation results for three 650 V Si SJMOS and SiC SBD pairs with different current ratings provide validation of the proposed analytical model.

关键词： MOSFET   Mathematical models   Frequency modulation   Optimization   Voltage control   Steady-state   Switches   Control variable optimization   electric vehicle (EV)   generalized harmonic approximation (GHA)   phase-shift and duty-ratio (PSDR) control   three-port resonant converter (TPRC)   triple active bridge  

摘要： Isolated three-port dc-dc converters (TPCs) facilitate integration of three voltage sources/loads in electric vehicle applications. Three-port resonant converter (TPRC) is an attractive TPC topology as it inherits the advantages of resonant converters. Phase-shift (PS) control applied to TPRCs enables independent power flow control among all ports. Phase-shift and duty-ratio (PSDR) control introduces three additional degrees of freedom providing the potential for improving the converter efficiency compared to PS control. This article presents a generalized harmonic approximation-based steady-state mathematical model for a TPRC with five-variable PSDR control. Mathematical solutions to the steady-state converter bridge voltages and the ac currents under PSDR control are provided. The proposed mathematical model is integrated with a TPRC power loss model and together are used to formulate a control optimization problem for evaluating the optimal control variables at maximum converter efficiency. The optimized five-variable PSDR control is compared against PS control using a 6 kW/100 kHz rated hardware demonstrator, with efficiency improvements as high as 12.4%.

关键词： Noise   Electrons   Transistors   Switches   MOSFET   Capacitors   Timing   1/f noise   CMOS image sensor (CIS)   high dynamic range (HDR)   shift biasing  

摘要： In this article, a noise improvement anddynamic range (DR) enhanced CMOS image sensor (CIS),using a shift biasing structure, is proposed. The shift bias-ing pixel is constructed from a conventional 4T pixel andthree additional transistors, including a bias transistor (BT)and two switch transistors. The BT works as a switch toconnect the source and drain to accumulate electrons inthe source follower (SF) in shift biasing mode and providesan extra capacitance to enlarge the capacity of floatingdiffusion (FD) in low gain (LG) mode. Electron distributionand noise performance of SF are simulated to prove thefunction of shift biasing pixels. A prototype sensor, witha 512x128-pixel array, is fabricated with a 180 nm CISprocess. Measurement shows a temporal noise of 2 e-isachieved, which is a 2 e-noise improvement comparedwith the reference 4T readout mode of shift biasing ***, an over 92 dB DR is realized by combiningshift biasing mode and LG mode without any specific pro-cess or complex control circuits

关键词： Field effect transistors   Diamonds   Logic gates   MOSFET   Logic circuits   Logic   Inverters   Diamond   directly coupled hydrogen terminated diamond FET logic (DCHDFL)   inverter   high gain   high-temperature  

摘要： The directly coupled hydrogen-terminated diamond FET logic (DCHDFL) circuit is fabricated. The E-mode and D-mode FETs are assigned as driver and load devices of the DCHDFL circuit to achieve inversion characteristics. The E-mode FET showcases high I-DSmax of 53.3mA/mm, V-TH of -0.8 V, low SS of 98 mV/dec and on/off ratio of 10(9), which enable input/output logic level matching with a low drive/load ratio of 1.0. The peak gain of circuit increases from 12.57 to 36.3 V/V with V-DD ranging from -5 V to -25 V, which is the highest gain achieved of diamond inverters, due to the high on/off ratio and low SS of E-mode FET. This circuit exhibits proper functions up to 200 degrees C, demonstrating a good thermal stability. These results indicate the great potential and possibilities for diamond smart power integrated circuit application.