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关键词： Logic gates   Wires   Stress   Silicon carbide   MOSFET   Voltage measurement   Thermomechanical processes   Failure detection   gate open-circuit failure   internal gate state   internal gate state   gate open-circuit failure   internal gate state   SiC MOSFETs   Logic gates   Wires   Stress   Silicon carbide   MOSFET   Voltage measurement   Thermomechanical processes  

摘要： Gate open-circuit failure caused by cracking and liftoff of gate bond wires has been demonstrated to be a new failure mode of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (mosfets), which can cause serious consequences such as shoot-through fault and gate-oxide breakdown. To enhance the reliability and robustness of SiC mosfets, a fast and accurate detection scheme for such failure is required. This article proposes a gate open-circuit failure detection method based on the extraction of the internal gate state. Although this state is unavailable externally, it can be extracted from gate current pulses. The gate open-circuit failures are then detected by checking the inconsistency between the drive signal and the internal gate state. Experimental results validate that the proposed method can accurately detect all types of gate open-circuit failures within 55 ns.

关键词： Logic gates   Degradation   Silicon carbide   Junctions   Temperature measurement   Monitoring   MOSFET   Gate-oxide degradation   junction temperature   monitoring   silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs)   temperature-sensitive electrical parameters (TSEPs)  

摘要： The online accurate junction temperature monitoring improves the reliability of power converters throughout the lifetime of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFETs). Without the correction, the methods based on the temperature-sensitive electrical parameters (TSEPs) immune to packaging degradation have low accuracy for SiC MOSFETs with the gate-oxide degradation. Without shutting down the power converters, an online correction method is proposed by measuring the turn-on delay time and the specific charge time of input capacitance. The turn-on delay time is used to monitor the junction temperature. The specific charge time of input capacitance is used to characterize the gate-oxide degradation state. The junction temperature of the device under test (DUT) is monitored by the relationship between the turn-on delay time and the junction temperature of twin device (TD) in the same degradation state as the gate oxide of the DUT. The junction temperatures of SiC MOSFETs with different degradation states of gate oxide are accurately monitored online based on the buck converter. The monitoring error of junction temperature is one order of magnitude smaller than the uncorrected one. The accurate online monitoring of junction temperature for degraded SiC MOSFETs can be achieved.

关键词： MOSFET   Silicon carbide   Logic gates   Resistance   Frequency measurement   Power measurement   Electrical resistance measurement   Switches   Silicon   Impedance   Fast switching events   input impedance   internal gate resistance   silicon carbide (SiC) power MOSFETs  

摘要： This article presents an analysis of the internal gate resistance of silicon carbide (SiC) power MOSFETs and its influence on the dynamic device performance. The internal gate resistance of SiC power MOSFETs features a frequency and voltage dependency that is not observed for silicon (Si) power MOSFETs, and hence, not investigated in mature Si device technology. Using numerical device modeling based on experimental electrical characterization, the low-frequency (LF) behavior of the internal gate resistance is attributed to the defects at the SiC-oxide interface. The high-frequency (HF) behavior is explained by the gate signal propagation across the die area and incorporated in a proposed MOSFET model. In the example of a reference SiC power MOSFET design, the developed model is used to evaluate the differences between the simulated and the measured switching waveforms in more detail. The results do not only reveal the physics of the internal gate resistance of SiC power MOSFETs but also highlight how the standard SPICE models, which include the internal gate resistance as a lumped resistor, can be limited in modeling the switching waveforms of SiC power MOSFETs and estimating switching losses with high accuracy.

关键词： SiC MOSFETs   single-event burnout (SEB)   single event gate rupture (SEGR)   reliability   on-resistance  

摘要： Heavy ion strike-induced Single-Event Effect (SEE) is an essential reliability issue for SiC MOSFETs in radiation environments. The mass clustering of excess charges in SiC MOSFET is found to be root cause for device failure when heavy ion strikes. Based on the SEE failure mechanism, a planar gate SiC MOSFET with Hole Extraction Channel (HEC-MOS) and current aperture structure to improve its SEE immunity and electrical performance is proposed in this paper. The embedded P+ pillar provides an additional path to extract excess holes during heavy ion radiation so that transient currents and SEE response time are greatly reduced. As a result, the maximum lattice temperature (hot spot) decreases by 768K, and a single-event burnout (SEB) threshold voltage of 624V is achieved with linear energy transfer (LET) value of 75MeV center dot cm(2)/mg for HEC-MOS, which is 1.4 times higher than conventional SiC MOSFET (Conv-MOS). Moreover, the gate oxide electric field also decreases similar to 10 times owing to much less clustered holes in JFET region, which ensures HEC-MOS superior immunity to single-event gate rupture (SEGR). Apart from improving SEE performance, a better trade-off with its electrical performances is also considered. By adopting optimized parameters in current spreading layers and P+ pillar, the specific ON-resistance of HEC-MOS is reduced by 17.5% while maintain a good forward blocking capability and SEB immunity. Therefore, HEC-MOS is a promising candidate for harsh environmental applications.

关键词： SiC MOSFET   Gate oxide degradation   DM EMI   Amplitude-frequency characteristics  

摘要： This paper investigates gate oxide degradation and its influence on Differential Mode(DM) EMI signals. The study reveals that changes in the parasitic capacitance within the chip, resulting from gate oxide degradation, can modify the amplitude-frequency characteristics of DM EMI signals, leading to unexpected transmission outcomes. This paper subjects SiC MOSFET modules to periodic high-temperature gate bias stress, extracts the spectrum characteristics of DM EMI, and assesses the impact of junction temperature. The analysis explores the impact of gate oxide degradation on low and high frequency DM EMI signals. Experimental results reveal distinct sensitivities of amplitude-frequency characteristics in the DM EMI signals to temperature variations and responses to gate oxide degradation at various frequency bands. The extrapolation of the correlation between the frequency-domain characteristics of the DM EMI signals and the degree of gate oxide degradation introduces a novel approach to evaluate the lifespan of power electronic devices.

关键词： Meminductor   Memristor   Emulator   Chaotic oscillator   Pinched hysteresis loop   Chua's circuit  

摘要： In this paper, a grounded meminductor emulator has been proposed using six MOSFETs (3NMOS and 3PMOS) only. Three transconductance stages and two capacitors are generally required to realize a meminductor emulator. Meminductor is considered as an inductor having memory. In the proposed design of meminductor emulator, the gyrator circuit is realized using common-source and common-gate amplifiers with one capacitor. The first capacitor is used to obtain the behaviour of inductance while the second capacitor is used for charge storage which acts as a memory element. In the proposed design of meminductor emulator, the gate-to-source capacitor of MOSFET is utilized in place of external capacitor for memory element. Therefore, the proposed design is free from the requirement of passive components as the required capacitor is formed by MOSFET. Also, the frequency characteristics of proposed meminductor are found to be satisfactory up to 100 MHz. The other essential characteristics such as non-volatility test, temperature analysis, tunability, Monte Carlo, and corner analysis are also found to be satisfactory. The proposed design of meminductor emulator is compared with other existing meminductor emulators. The performance of the emulator is successfully verified through the realization of chaotic oscillator circuit.

关键词： MOSFET   4H-SiC   bias temperature instability (BTI)   hole trap   hole trap   MOSFET   hole trap   nitric-oxide (NO) annealing   nitric-oxide (NO) annealing   time- dependent dielectric breakdown (TDDB)  

摘要： Reliability challenges persist with silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) in power electronic applications due to low oxide quality. There are still some issues, such as low mobility, bias temperature instability (BTI), and low lifetime in it. Nitric-oxide (NO) postoxidation annealing is a key technology to achieve high mobility. In this study, we investigate how different annealing processes impact the time-dependent dielectric breakdown (TDDB) reliability of SiC MOSFET devices and explore the reasons for changes in device lifetime under NO passivation. Through X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS) profile analysis, the element distribution and chemical bonds under various annealing conditions were tested. A clear conclusion shows that the trap density and distribution are main reason affecting the device long-term reliability. The study reveals that different defect distributions lead to differing degrees of impact ionization and electron tunneling in the TDDB. Notably, high temperature with short-time NO annealing under the same oxidation significantly increases the long-term reliability of SiC MOSFET devices without reducing the device mobility or deteriorating the BTI effects.

关键词： Power MOSFETs   Silicon-germanium (SiGe)   Heterojunction   Reverse recovery   Reverse conduction  

摘要： -A novel power MOSFET structure with Drain-side N-Si/N-SiGe Heterojunctions (DH-MOS) is proposed by introducing a N SiGe region which is sandwiched between the N-drift region and N+ substrate on the drain side. The operation mechanism and simulation verification of DH-MOS are presented. Due to the difference in valence band of N Si/N SiGe heterojunction, holes can be more easily expelled from the N-drift region into N SiGe region during the reverse conduction of DHMOS, resulting in a significant reduction in hole density inside the N-drift region, thus improving the reverse recovery performance. Simulation results show that the reverse recovery charge (Qrr) of DH-MOS is 2.08 mu C/cm2, approximately 66.34 % lower than the 6.18 mu C/cm2 of conventional MOS. The introduction of new DH-MOS structure with N-Si/N-SiGe heterojunctions does not result in a significant increase in reverse conduction voltage (VF). In addition, it does not sacrifice any forward conduction and blocking characteristics. The proposed DH-MOS introduces changes on the drain side, unlike existing methods which focus on the source side or drift region. And it can be compatible with existing improving measures to further improve the reverse recovery performance.

关键词： Total ionizing dose   Single event gate rupture   Synergistic effect   VDMOS with stacked layers   TCAD simulation  

摘要： The synergistic effect of total ionizing dose on single event gate rupture (SEGR) was simulated in the vertical double diffusion metal oxide semiconductor device with SiO2-Si3N4 stacked gate layer. In comparison to the device with a single SiO2 gate layer, the synergistic effect was revealed to be suppressed in the device with SiO2-Si3N4 stacked layer. The mechanism is that the oxide layer is a sensitive area of the SEGR effect. Compared with the single SiO2 layer, the superposition of the additional electric field formed by the trapped holes in the sensitive area of the stacked layer leads to a decrease in the sensitivity of the synergistic effect, which is more obvious with increasing the volume of the Si3N4 layer.

关键词： Mathematical models   Transient analysis   Integrated circuit modeling   Switches   Numerical models   Solid modeling   Semiconductor device modeling   Electromagnetic (EM) field   fully coupled model   switching transient   time domain  

摘要： For power electronics systems, the switching transient is critical for efficient and reliable energy conversion. While the electromagnetic (EM) field simulation is instrumental in analyzing switching transients, the simulation is complicated due to the voltage and current's complex distribution and their rapid changes. This article proposes a space partition and time domain decoupling method to model and simulate the 3-D fully coupled EM fields on the time domain for the switching transient, specifically simulating a SiC MOSFET turn-off transient. The space is partitioned into four modules based on different dominant feature in different materials, enhancing the model's numerical stability. Then the time domain decoupling strategy implements staged solving from independent modules to the fully coupled model, effectively coping with the challenges caused by complex coupling relations. We design the spatial fast-changing EM field measurement experiment to validate the model and method's accuracy. The proposed model reveals EM field dynamics during the transient and holds promise for facilitating practical power electronics design, such as the design of EM compatibility (EMC).