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关键词： SiC   MOSFET   Charge pumping   Vth shift   Interface  

摘要： This work focuses on the extraction of Threshold Voltage Shift due to interface trapping from Charge Pumping (CP) measured curves. The proposed mathematical approach analyzes the peak of the charge pumping curve, proportional to the average interface defects density, for estimating the threshold voltage shift due to interface trapping separately from the shift induced by oxide trapping. The high-frequency nature of CP measurements is therefore exploited for the detection of fast states. The analyzed devices are 4H-SiC n-channel MOSFETs and a custom, on-wafer, in-situ measurement setup is used. Under constant current gate stress, positive and negative charge trapping processes are identified;the role of a) charge trapping in the oxide and b) interface states generation is analyzed and described.

关键词： Nanoprobing   MOSFET   Heavy doping missing defect   SCM  

摘要： The paper demonstrates an effective flow to localize heavy doping missing defect accurately in failed metaloxide-semiconductor field-effect transistor (MOSFET). It is commonly known that it is not feasible to localize rare doping anomaly and further visualize the corresponding less doped regions in MOSFET relying on ordinary transmission electron microscopy (TEM) analysis since the dopant distribution is not detectable for TEM. Nevertheless, we found that this kind of defect can be isolated by the combined use of nanoprobing analysis and scanning capacitance microscopy (SCM) technique. The combinational solution was rarely reported before. Nanoprobing analysis of transfer characteristic of failed MOSFET confirms the on-state current drop by two orders of magnitude. Next, the contacting state at source and drain region of MOSFET is examined. Currentvoltage (I-V) characteristic of source and drain p-n junctions indicates that high contact resistance comes from metal-semiconductor interface change from ohmic contact to rectifying contact unexpectedly. Eventually, intensive analysis of SCM data proves that tungsten plugs touch lightly doped silicon so that the outcome leads to the formation of Schottky junction that owns rectifying I-V characteristic. In contrast, the tungsten plug touching heavily doped silicon produces ohmic contact, so it keeps normal I-V characteristic of p-n junction. Energy-band theory explains that I-V characteristic of metal-semiconductor interface is closely related to doping concentration in silicon since it determines the potential barrier width at interface where mobile carrier transport phenomenon occurs. The potential barrier width increases as the doping concentration decreases in the silicon side of the interface. We conclude that lack of heavy doping in MOSFET source and drain areas is responsible for high contact resistance. In the article, we present several practical examples to show accurate localization of heavy doping missing defe

关键词： Logic gates   Switches   Three-dimensional displays   HEMTs   Integrated circuit interconnections   JFETs   Control systems   Voltage control   Silicon carbide   MOSFET   SiC JFET   GaN HEMT   3-D package   switching speed  

摘要： To unlock the full fast-switching potential of the GaN-HEMT/SiC-JFET cascode device, parasitic interconnection inductances are minimized with a 3-D stacked co-packaging configuration. This configuration offers the benefits of reduced switching loss and suppressed oscillation. Equipped with the 3-D co-package configuration, the dv/dt control capability of the GaN/SiC cascode device is enhanced by introducing an additional gate-drain capacitor, CGD-LV, to the low-voltage GaN HEMT. This additional CGD-LV improves the coupling between the input control gate voltage and the JFET's gate voltage, which ultimately determines the switching speed of the GaN/SiC cascode device. Experimental results verified the GaN/SiC cascode device, when equipped with the 3-D co-packaged configuration and the additional CGD-LV, demonstrated fast switching capability with adequate dv/dt control.

关键词： Transistors   Logic gates   Voltage measurement   Semiconductor device modeling   HEMTs   Gallium nitride   Capacitance   Silicon   MOSFET   Switching circuits   Gallium nitride (GaN) devices   hybrid-drain-embedded gate injection transistor (HD-GIT)   behavioral model  

摘要： Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs), with their superior on-resistance and switching times, provide a promising alternative to Silicon (Si) and SiC devices. Commercially available normally offGaN transistors can be categorized into two main groups: hybrid transistors, which incorporate a Si mosfet, and e-mode transistors. The latter are the most promising GaN transistors, as they do not have the limitations of Si mosfets. Currently, there are two commercial e-mode transistors: the Schottky Gate (SG) p-GaN and the HD-GIT (Hybrid-Drain-embedded Gate Injection Transistor) transistors. However, they differ from the gate terminal standards that have been defined for years by Silicon IGBTs and mosfets (lower threshold voltage, nonconstant Miller plateau, etc.), complicating their adoption in power electronics converters. This is particularly true for the HD-GIT transistor, which diverges from standard mosfet gate operations due to its nonisolated gate terminal. To aid application engineers in understanding these devices and facilitating their adoption in real power applications, simulation models are useful tools. However, there are no simple HD-GIT transistor models that can be easily parameterized by application engineers. Therefore, in this work, an experimentally verified behavioral model of an HD-GIT transistor is presented and described.

关键词： Coils   Protection   Bandwidth   Silicon carbide   MOSFET   Frequency measurement   Resonant frequency   Gain   Current measurement   Broadband communication   Drift and droop errors   high bandwidth   medium-voltage (MV) SiC mosfet   overcurrent protection   Rogowski coil  

摘要： To guarantee safe switching of the expensive medium-voltage (MV) device with limited durability, the overcurrent protection scheme based on Rogowski coil current sensor (RCCS) is the promising method, featuring fast response and galvanic isolation. However, it is an inherent contradiction to achieve the RCCS with both high noise immunity and high-bandwidth capabilities. In addition, the nonideal dc and low-frequency characteristics of the integrator cause drift and droop errors. In this article, to address the aforementioned challenges, the broadband RCCS is developed and integrated into the overcurrent protection circuit for the MV SiC mosfet. The novel coil is designed based on the transmission line theory to overcome the constraints imposed by parasitic components on bandwidth. The proposed coil achieves an extra-high bandwidth of approximate 300 MHz with high mutual inductance and shielding layers for high noise immunity. Furthermore, the broadband integrator design method with low-frequency attenuation is proposed to eliminate drift and reduce droop errors significantly. Based on the developed RCCS, the proposed overcurrent protection circuit reacts to both the fault under load and hard switching fault rapidly and softly turns off the device within merely 200 ns. Comprehensive experiments demonstrate its exceptional potential in monitoring current and protecting the expensive MV devices.

关键词： MOSFET   Logic gates   Switching loss   Resistance   Capacitance   Voltage   Switching frequency   Switches   Transient analysis   Internet of Things   Analog-digital integrated circuits   DC-DC power converters   Low power electronics   Monolithic integrated circuits   Power MOSFET   Power system management   Power integrated circuits   PMICs   Switched mode power supplies  

摘要： This article presents a novel mixed-signal architecture for the extraction and online tracking of the maximum efficiency point in generic integrated dc-dc converters, called power segmentation optimum. This optimal condition is achieved by dynamically adjusting the size of the power switches to minimize total losses. Proposed system continuously tracks the optimal efficiency point under all operating conditions, adapting to both external factors (such as input/output voltage, switching frequency, temperature, and output current) and internal parameters (such as mosfet on-resistance, and gate capacitance). The operating principle consists in a A/D mixed signal implementation which continuously extracts and compares a proportional value of each loss contribution, deriving the corresponding configuration which minimizes the total losses. This technique is particularly suitable for IoT applications, characterized by long idle periods and high current pulse transients. In order to validate the theoretical results, proposed method is implemented inside a 5 A dc-dc fullyintegrated buck converter realized in 180 nm technology with 5 V input voltage rating and switching frequency up to 4 MHz.

关键词： Logic gates   Inductance   Threshold voltage   MOSFET   Silicon carbide   Resistance   Aging   Transient analysis   Switches   Stress   Asymmetric layout   current sharing   parallel connection   silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs)   stray inductance   threshold voltage  

摘要： For high-capacity applications, paralleling multiple silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfets) is essential. However, it is challenging to achieve complete symmetry in the gate circuits of parallel devices, resulting in mismatched gate inductances, which may lead to the current imbalance. This article focuses on investigating the evolution of threshold voltage dispersity under mismatched gate inductances and its impact on the current sharing evolution. It is found that mismatched gate inductances cause the threshold voltage dispersity to increase with gate stress time, thereby inducing a deterioration in current sharing. A boost converter with two devices in parallel was tested, demonstrating that the difference in the minimum turn-off gate voltage including undershoot is the primary trigger for increased threshold voltage dispersity. Besides, an off-state gate voltage optimization strategy was proposed to effectively mitigate the increase in threshold voltage dispersity and improve the evolution of current sharing under mismatched gate loop inductances. The findings are intended to improve the performance of SiC mosfets in parallel applications.

关键词： Ga2O3   MOSFET   superjunction   self-biased   specific on-resistance   breakdown voltage  

摘要： In this article, a high-performance enhancement-mode (E-mode) lateral superjunction (SJ) beta-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a self-biased p-type nickel oxide (NiO) layer was proposed and numerical investigated. The drift region of the proposed lateral SJ Ga2O3 MOSFET includes n-type Ga2O3, Al2O3 and p-type NiO layers. The electric field distribution and specific on-resistance of the drift region both are greatly improved, due to the compensation effect n-type Ga2O3 and p-type NiO SJ drift layers. Additionally, the p-type NiO layer is self-biased with a voltage of -14.3 V, to form an accumulation layer in the drift region, which further reduces the specific on-resistance (R-on,R-sp) of the device. Simulation results indicated that the proposed device achieves a breakdown voltage (BV) of 7000 V and R-on,R-sp of 17.73 m Omega cm(2). In contrast, the conventional device with the same drift region length has a BV of 3500 V and R-on,R-sp of 162.58 m Omega cm(2). The figure of merit values for the proposed and conventional devices were 2.76 GW cm(-2) and 75.34 MW cm(-2), respectively, representing a 3565% improvement. The combination of superior device performance and a straightforward manufacturing process presents a promising outlook for the application of the proposed device.

关键词： Strain measurement  

摘要： Evaluating the mechanical performance and operational conditions of bridge structures relies on accurately measuringement of vibration displacement. Such measurement can provide essential parameters, such as mode and frequency, to assess the operational status and condition of damaged bridge structures. However, traditional displacement monitoring techniques have high cost, low accuracyare expensive, have low accuracy, and offer and limited measurement positions. This paper proposes a A low-cost, non-contact, and multi-point measurement method was proposed in this paper,based on the Kernelized correlation filters (KCF) algorithm to measure the vibration displacement of bridges. The proposed method used shaking Shaking table tests on a dual-column pier model were conducted,with energy dissipation links under different white noise sweeps. The recorded vibration displacement from a laser displacement sensor (LDS) was used as a reference for comparison. The natural frequencies and mode shapes of the dual-column pier and bridges were identified using the covariance-driven stochastic subspace identification method. The study verified the The reliability, feasibility, and accuracy of machine vision technology in identifying the natural frequencies and mode shapes of bridges were verified. The results showed that the small amplitude vibration displacement of the dual-column pier identified by the KCF algorithm is almost consistent with the waveforms, change trends, and peak values recorded by LDS, with a maximum peak error of 4%. The error between the natural frequencies identified by the KCF algorithm and the LDS results was within 2.5%. The confidence level of the mode shapes identified between both approaches was above 0.90. © 2025 Chinese Vibration Engineering Society. All rights reserved.

关键词： Triple metal and quadruple metal gate work function engineering, Double surrounding gate   Inversion mode   Si Nanotube MOSFET   NEGF   I-D   SS   DIBL  

摘要： In this work, Triple Metal (TM) and Quadruple Metal (QM) gate engineering have been done for both junctionless (JL) inversion mode (IM) and Double surrounding Gate (DSG) Si nanotube (SiNT) MOSFET to study drain current (I-D) characteristics for gate length of 2 nm using Silvaco ATLAS 3D TCAD. For this, the Non Equilibrium Green's Function (NEGF) method has been used along with self-consistent solution of Schrodinger's equation with Poisson's equation. In case of IM channel region of SiNT device, there is lightly doping. In this device SiO2 is used as gate oxide thickness of 0.8 nm, with Si channel radius of 1.5 nm have been used. A comparison has also been done between results of TM DSG and QM DSG SiNT. For a reasonable comparison between JL and IM SiNT, in each case of TM and QM JL SiNT doping concentration are optimized for two goals (i) to obtain the same I-ON as IM SiNT and (ii) to obtain the same threshold voltage (V-TH) as IM SiNT. This results in about 10 times smaller I-OFF for both JL, I-ON and V-TH matching SiNT for both TM and QM case. This also results in about 10 times higher I-ON/I-OFF current ratio for all JL device as compared to IM device for both TM and QM case. All used JL SiNT results in smaller DIBL in both TM and QM case as compared to IM SiNT device. In this work for JL SiNT, a smaller DIBL similar to 36.46 mV/V, nearly ideal subthreshold slope (SS) similar to 60 mV/dec, and higher I-ON/I-OFF current ratio similar to 4.41 x 10(10) have been obtained in comparison to available literature CGAA device results.