课程文献中心 更多>>

关键词： Silicon carbide   Capacitance   MOSFET   Mathematical models   Numerical models   Voltage   Analytical models   Current spikes   model   silicon carbide (SiC) MOSFET   turn-on   voltage spikes  

摘要： All silicon carbide (SiC) devices have the advantages of high switching speed and low loss. The current slew rate di/dt, current and voltage spikes, oscillation current/voltage, and turn-on loss (DOSs) are important electrical indicators for power devices during the switching process. However, there are few analytical expressions that balance accuracy and simplicity for quantitative analysis of DOSs due to nonlinear issues. This article derives the linearized analytical expressions for DOSs and analyzes the sensitivity of current and voltage spikes to different parameters during the turn-on process based on a piecewise linearization method. The analytical expressions provide an intuitive description of the relationship between DOSs and different parameters. For example, the phenomenon where voltage spikes of the high-side device do not monotonically decrease with the increase of driving resistance is discovered and explained. The sensitivity offers guidance for accurate and simplified linear processes in DOS calculations. The simplified equivalent output capacitance method and accurate dynamic current slew rate are proposed in the linearization process, as the current and voltage spikes have low sensitivity to output capacitance and high sensitivity to the current slew rate. The piecewise linearization method for calculating DOSs is verified by double pulse test (DPT) experiments and the relatively optimal driving resistance is designed and discussed.

关键词： MOSFET   Electric fields   Logic gates   Ions   Schottky diodes   Heterojunctions   Silicon   Heterojunction diode (HJD)   power MOSFET   reverse recovery   single-event gate rupture (SEGR)  

摘要： A novel structure of retrograde p-well Schottky source MOSFET with integrated Si/SiGe heterojunction diode (RP-HJD-S-MOS) is proposed by introducing a p-SiGe region at the center of the device's source side. During the heavy-ion striking of RP-HJD-S-MOS, the p-SiGe region can help expel holes, thereby reducing the number of holes accumulated below the gate oxide layer and improving resistance to single-event gate rupture (SEGR). In addition, when the device operates in a reverse conductive state, the heterojunction diode has a lower barrier height of the electron compared with the parasitic PiN body diode. It can provide an additional electron current path, which turns on before the PiN diode and effectively suppresses the minority carrier injection from the PiN body diode, thereby improving the reverse recovery characteristics of the device. The TCAD simulation results show that under the same irradiation conditions, the SEGR resistance of RP-HJD-S-MOS is stronger than that of RP-SSBR-S-MOS. In addition, the reverse recovery charge of the novel structure is 2.702 mu C/cm(2) , reduced by 39.1% compared to RP-SSBR-S-MOS.

关键词： Voltage   In-memory computing   Random access memory   Neural networks   MOSFET   Energy efficiency   Computational modeling   SRAM   compute-in-memory (CIM)   quantized neural networks   multiply and accumulate (MAC)   zero-skipping   current-mode accumulation  

摘要： This article presents a novel dual 7T static random-access memory (SRAM)-based compute-in-memory (CIM) macro for processing quantized neural networks. The proposed SRAM-based CIM macro decouples read/write operations and employs a zero-input/weight skipping scheme. A 65nm test chip with 528x128 integrated dual 7T bitcells demonstrated reconfigurable precision multiply and accumulate operations with 384 x binary inputs (0/1) and 384 x128 programmable multi-bit weights (3/7/15-levels). Each column comprises 384 x bitcells for a dot product, 48 x bitcells for offset calibration, and 96 x bitcells for binary-searching analog-to-digital conversion. The analog-to-digital converter (ADC) converts a voltage difference between two read bitlines (i.e., an analog dot-product result) to a 1-6b digital output code using binary searching in 1-6 conversion cycles using replica bitcells. The test chip with 66Kb embedded dual SRAM bitcells was evaluated for processing neural networks, including the MNIST image classifications using a multi-layer perceptron (MLP) model with its layer configuration of 784-256-256-256-10 The measured classification accuracies are 97.62%, 97.65%, and 97.72% for the 3, 7, and 15 level weights, respectively. The accuracy degradations are only 0.58 to 0.74% off the baseline with software simulations. For the VGG6 model using the CIFAR-10 image dataset, the accuracies are 88.59%, 88.21%, and 89.07% for the 3, 7, and 15 level weights, with degradations of only 0.6 to 1.32% off the software baseline. The measured energy efficiencies are 258.5, 67.9, and 23.9 TOPS/W for the 3, 7, and 15 level weights, respectively, measured at 0.45/0.8V supplies.

关键词： Impact ionization  

摘要： 1. AbstractThe floating body (FB) Effect in Partially Depleted (PD) Silicon-on-Insulator (SOI) devices has traditionally been perceived as a concern due to its potential to induce variations in device performance. However, this phenomenon presents unique opportunities for enhancing energy efficiency. Also, the ability of the floating body (FB) to modulate threshold voltage facilitates improved headroom in analog circuit design, enabling enhanced performance and functionality for low-voltage applications. By highlighting the untapped potential of this well-established technology, we propose a novel FB Potential model considering impact ionization (II) and Self-Heating (SH) effects for low terminal bias (VDS and VGS). Subsequently, the proposed FB potential model is then utilized to develop a model for small signal parameters (gm and Ro) of a PD SOI device. © 2024, The Authors. All rights reserved.

关键词： 高功率微波   半导体器件   失效和防护  

摘要： 高功率微波是通过直接及间接的耦合方式产生电热效应,会在不同程度上对电子通信设备产生干扰,导致设备出现无法逆转的损伤.本文重点分析高功率微波作用下半导体器件失效问题,对集中不同列的晶体管受到高脉冲影响产生的变化进行分析,提出了瞬态稳压抑制器的优化方式,有利于半导体器件失效防护.

关键词： 220kV油浸式变压器   全面试验方案   设计   优化  

摘要： 本文首先介绍了全面试验的重要性,以及设计和优化试验方案的目的;然后依据设计原则再结合变压器设备的特点和需求,提出了合理、全面、高效的试验方案设计与优化思路;接着针对试验参数的选择、试验序列的安排、试验仪器的选择等进行了详细讨论;最后强调通过科学有效的试验方案设计与优化,可以提高试验的准确性、可靠性和效率,为电力系统的设备运行提供技术支持和保障.

关键词： MOSFET   Thermal characteristics   Soldering   Reinforcements   Titanium oxide   Reliability   Shear strength  

摘要： Purpose - This paper aims to investigate the influence of composite solder joint preparation on the thermal properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the mechanical strength of the soldered joint. Design/methodology/approach - Reinforced composite solder joints with the addition of titanium oxide nanopowder (TiO2) were prepared. The reference alloy was Sn99Ag0.3Cu0.7. Reinforced joints differed in the weight percentage of TiO2, ranging from 0.125 to 1.0 Wt.%. Two types of components were used for the tests. The resistor in the 0805 package was used for mechanical strength tests, where the component was soldered to the FR4 substrate. For thermal parameters measurements, a power element MOSFET in a TO-263 package was used, which was soldered to a metal core printed circuit board (PCB) substrate. Components were soldered in batch IR oven. Findings - Shear tests showed that the addition of titanium oxide does not significantly increase the resistance of the solder joint to mechanical damage. Titanium oxide addition was shown to not considerably influence the soldered joint's mechanical strength compared to reference samples when soldered in batch ovens. Thermal resistance Rthj-a of MOSFETs depends on TiO2 concentration in the composite solder joint reaching the minimum R-thj at 0.25 Wt.% of TiO2. Research limitations/implications - Mechanical strength: TiO2 reinforcement shows minimal impact on mechanical strength, suggesting altered liquidus temperature and microstructure, requiring further investigation. Thermal performance: thermal parameters vary with TiO2 concentration, with optimal performance at 0.25 Wt.%. Experimental validation is crucial for practical application. Experimental confirmation: validation of optimal concentrations is essential for accurate assessment and real-world application. Soldering method influence: batch oven soldering may affect mechanical strength, necessitating exploration of alternative methods. Ther

关键词： Circuit design   design methodology   geometric programming   MOSFET model  

摘要： The design of analog integrated circuits is a demanding task that involves many constraints and objectives. Also, the transistor models employed must consider high-order physics effects to achieve accurate solutions. Geometric Programming (GP) allows finding the global minimum in optimisation problems, but requires design equations to be in monomial or posynomial form. This work proposes a simplified model inspired on the Advanced Compact MOSFET model tailored to be used in GP problems. The proposed model considers short-channel effects and it is valid in the saturation region with all inversion levels. The equations are presented, first showing the transistor current-voltage characteristic and then the associated capacitances. The validity of the equations is proven by their capacity to fit to the simulated data, achieving a mean error of 0.4% for the main NMOS characteristic. After that, the optimal design of two basic amplifier stages is performed to demonstrate the model usability with GP. The predicted voltage gain and bandwidth of the designed amplifiers are compared with simulations, presenting mean errors of 24.7% and 31.7%, respectively. These errors are low when viewed from a logarithmic perspective and considering the wide design space covered. As GP optimisation guarantees the global minimum location and does not require the usage of a circuit simulator in the loop, the proposed GP-friendly compact model can enable fast and accurate optimisation of analog integrated circuits.