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关键词： Degradation   Neurons   Stress   MOSFET   Silicon-on-insulator   Logic gates   Temperature measurement   Semiconductor device measurement   Current measurement   Thermal stresses   Band-to-band-tunneling (BTBT)   on regime (I-ON)   reliability   silicon on insulator (SOI)   spiking neural network (SNN)   subthreshold (SS) regime  

摘要： Low-power operations are essential for implementing large spiking neural networks (SNNs) in real-world applications. An area and energy-efficient demonstration of a functional liquid state machine (LSM) for spoken word detection using the band-to-band-tunneling (BTBT)-based neuron was proposed earlier. For a product-level demonstration of the BTBT regime operating chips, the variability and reliability of neurons emerge as noteworthy concerns for neuromorphic processors due to the potential implications for performance degradation over time. In this work, we characterize and compare the reliability of partially depleted (PD) silicon on insulator (SOI) transistors in the BTBT and on-regime ( Undefined control sequence I-ON ) regimes. The drain current fractional degradation ( Delta I-D/I-D) increases with an increase in voltage and thermal stress in the BTBT and Undefined control sequence I-ON regime. The reaction-diffusion-drift (RDD) framework is used to estimate device degradation under operating bias conditions. At operating bias, a similar to 17% fractional degradation is observed in the BTBT regime operation for ten years, comparable to the degradation observed in the Undefined control sequence I-ON regime. Finally, we analyzed the impact of device degradation on the SNN performance.

关键词： MOSFET   power MOSFET   Schottky diodes   semiconductor device breakdown   semiconductor devices  

摘要： An improved 4H-SiC SBD-wall-integrated trench metal-oxide-semiconductor (SWITCH-MOS) with n-bury and split-gate is proposed. Under the premise of ensuring breakdown voltage (BV), the n-bury layer can smooth the path to current conduction, which reduces the specific on-resistance (RON, SP) and improves static characteristics. Besides, the split-gate is able to transform the gate-drain capacitance (CGD) and improve the dynamic characteristics. Therefore, a superior forward performance that SWITCH-MOS always craves is achieved. According to the simulation results, compared to the conventional SWITCH-MOS with almost the same BV, the proposed one reduces the RON, SP by 57% and the CGD by 59% while gaining equally advanced reverse performance. Its reverse conduction voltage is only -1.78 V, but its figure of merit reaches 1.67 GW/cm2 and 65 m OmeganC, which is attractive for the application in power inverters.

关键词： SiC MOSFET   Reverse conduction   Low switching losses   Bipolar degradation  

摘要： A novel asymmetric trench Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC MOSFET), featuring an integrated channel accumulation diode (CAD-MOS), has been proposed and investigated through numerical simulation. This innovative design aims to mitigate switching losses and eliminate the bipolar degradation of the body diode. The current spreading layer (CSL) channel, strategically positioned in the centre of the dummy gate, offers a low-barrier reverse conduction path. This represents a substantial advancement over the traditional PN body diode, significantly reducing the reverse conduction voltage drop from 2.84 V in the PN body diode to a mere 1.39 V in the CAD-MOS. Meanwhile, the reverse recovery charge of the CAD-MOS is reduced to 0.95 mu C/cm2, and the peak reverse recovery current stands at 45 A/cm2. Compared to conventional asymmetrical trench SiC MOSFET (CON-MOS), the CAD-MOS exhibits a 68.1 % reduction in reverse recovery charge and a 63.4 % decrease in peak reverse recovery current. The split-gate design also reduces the device gate to source capacitance (CGS), resulting in a 17.4 % reduction in total switching losses to 3.64 mJ/cm2. CAD-MOS also exhibits a reduced gate turn-on charge and demonstrates an enhancement in high-frequency figure of merit (HF-FOM) by 8.1 %.

关键词： MOSFET circuits   Stress   MOSFET   Transistors   SRAM cells   Degradation   Fluctuations   Hot carrier degradation (HCD)   lightly doped drain (LDD)   MOSFETs   quasi-ballistic transport   static random access memory (SRAM)   variability  

摘要： In this work, the impact of lightly doped drain (LDD) implantation doses on hot carrier degradation (HCD) variability behaviors has been studied for transistors and static random access memory (SRAM) cells. It is found that threshold voltage (V-T) variability is enhanced, while the saturation current (I-D) variability is suppressed for n-type MOSFETs (n-MOSFETs) and p-type MOSFETs (p-MOSFETs) during HCD. Nonuniform trap generation and the current self-convergence mechanism are used to explain the reason for variability, respectively. Devices fabricated at higher LDD doses have lower variability, which is attributed to improved quasi-ballistic transport characteristics. Furthermore, the impacts of HCD on the static noise margin (SNM) variability of SRAM cells in the hold and read state are also inhibited with the increased LDD doses due to the descending variability in individual transistors. Therefore, LDD process optimization is beneficial for transistors and circuits against HCD variability without additional design margin.

关键词： Circuits   Voltage   MOSFET   Capacitors   Power demand   Transistors   Generators   Voltage reference   energy saving   gain-boosting  

摘要： This brief presents a voltage reference circuit to greatly save the energy through four new techniques. (1) It uses a simple common-source amplifier to replace the complicated gain-boosted amplifier. Through using an additional capacitor, this simple common-source amplifier achieves an effective gain which is even higher than a gain-boosted amplifier. (2) It obviates the need for a differential amplifier, since it uses a special negative feedback structure. (3) The extra biasing circuit is no longer needed for the summing amplifier, which helps simplify the circuit structure. (4) MOSFETs in the sub-threshold region are used, which leads to a lower supply voltage. In a 180nm CMOS process, it achieves a 15nW power consumption, a 500mV minimum supply voltage, a 26.2ppm/degrees C average temperature coefficient (TC), and a 330 mu V/V line sensitivity. It realizes a 16 times reduction in the power consumption, when compared with the prior work that is based on a gain boosted amplifier.

关键词： Logic gates   MOSFET   Charge carrier processes   Voltage measurement   Germanium   Tunneling   Transistors   Silicon   Modulation   Latches   Back-gate (BG)   band-to-band tunneling (BTBT)   electrical modulation   impact ionization (II)   single transistor latch (STL)  

摘要： A single transistor latch (STL), driven by impact ionization (II) and band-to-band tunneling (BTBT), plays a crucial role in threshold switching in a thin-body MOSFET. The inherent challenge lies in the high latch-up voltage (VLU) LU ) required to trigger the STL because the II and BTBT mechanisms rely on higher voltages. Moreover, thus far, strategies for adjusting the V LU level have been limited to altering process parameters or materials that are difficult to change once decided. Therefore, these methods do not provide dynamic controllability of VLU. LU . The high V LU and lack of tunability limit and hinder various applications utilizing STL. In this study, V LU was experimentally reduced to near 1 V by asymmetric biasing, i.e., electrically separating the top of the body (ToB) and the bottom of the body (BoB) through front-gate (FG) biasing and back-gate (BG) biasing. The underlying physics of this reduction was elucidated by means of TCAD simulation through the analysis of energy band diagrams, II rates, and BTBT rates. A significant reduction in V LU was achieved solely through electrical modulation.

关键词： Electronic circuits for signal processing   CMOS amplifier   Integrated circuits   MOSFET   g(m)/I-D methodology  

摘要： This paper presents the analysis and design of CMOS differential amplifiers using the first-order approach and sizing the transistors with the g(m)/I-D methodology. The design of four amplifiers using 130 nm CMOS technology is shown, and through spice simulation basic concepts of performance and compliance specifications are verified. The comparison of the performance of the designed amplifiers, in the synthesis of an active low-pass filter, is made to show that the fundamental performance parameters of each amplifier, affects the expected performance of the circuit under design, showing that the CMOS amplifier is not general purpose but that the application takes advantage of the characteristics of the amplifier or, alternatively, the amplifier is designed to meet the requirements of the application. Finally, while each architecture is sized using the same general performance specifications, it is also true that each has a specific and unique overall performance. These differences can be obtained and understood with spice simulation, since the resources of the simulation tool are used properly. All results obtained are at room temperature.

关键词： Threshold voltage   Hysteresis   Radiation effects   Silicon carbide   MOSFET   Logic gates   Annealing   Oxide trapped charges   silicon carbide (SiC) MOSFET   threshold voltage hysteresis   total ionizing dose (TID) effect  

摘要： This work investigates the effects of total ionizing dose (TID) irradiation bias, temperature, dose, and post-irradiation annealing on the threshold voltage hysteresis of silicon carbide (SiC) MOSFETs. The research reveals that the TID effect decreases the threshold voltage hysteresis, which is proportional to the accumulation of radiation-induced charges in the gate oxide. The reduction in threshold voltage hysteresis is unrelated to the change of the interface-trapped charges. However, it is mainly caused by the reduction of the nonequilibrium interface trapped charge energy range (Delta E-VTH). The radiation-induced charges can exacerbate the hole emission process of the donor interface traps during the up-sweep process, which causes an upward shift of the lower boundary of Delta E-VTH . The slight shift of the Fermi energy level during the down-sweep process leads to no significant change in the upper boundary of Delta E-VTH . Eventually, the TID effect causes a reduction in the threshold voltage hysteresis. The changes in the occupation probability of the donor and acceptor interface traps during the scanning of the I-DS-V(GS )curves were extracted by TCAD simulation. The results showed that the inconsistent changes in the occupation probability of the donor interface traps in the up-sweep and down-sweep curves cause a reduction of the threshold voltage hysteresis. The analysis was further verified using different voltage sweep ranges in the experiment.

关键词： Noise   Logic gates   Couplings   Impedance   Silicon carbide   Integrated circuit modeling   MOSFET   Active gate driver (AGD)   common-source inductance   coupling noise   SiC mosfet  

摘要： The high switching speed of SiC mosfets is limited by the coupling noise in bridge-leg configurations. Conventional methods focus on the noise introduced by the gate-drain capacitance, which is suppressed by reducing the gate impedance with the active gate driver (AGD). However, when the common-source inductance (L-s) exists, noise spikes are not strictly increasing with gate impedance. The existing AGD parameter design methods have limited suppression effects. To fully utilize the noise suppression capability of AGD, this article constructs a noise mathematical model considering L-s, where the auxiliary branch is considered as RLC in series and the main factors affecting the coupling noise are all included. Based on the model, a parameter optimization algorithm is proposed. In detail, the noise spikes at different AGD parameters are calculated with a set of extracted switching characteristics. The proposed algorithm solves the AGD parameters with optimal noise suppression by using a designed cost function. The experimental results show that the variation trends of noise spikes at different AGD parameters can be accurately calculated. Compared with the conventional methods, the proposed algorithm suppresses noise spikes to optimal values. The optimization algorithm provides a guideline for the AGD parameter design.

关键词： Transistors   MOSFET   Logic gates   Silicon   Photonic band gap   Logic   Green's function methods   2-D material   field-effect transistor (FET)   logical applications   mid-frequency model   non-equilibrium Green's function (NEGF)   quantum transport   tight-binding (TB)  

摘要： A sub-nanometer field-effect transistor (FET) with MoSi(2)N(4 )as the channel material is investigated using non-equilibrium Green's function (NEGF) formalism for possible application in modern digital technology. The transistor input, output, and transfer characteristics are reported for 0.6 V supply. The output and transfer characteristics of the drain current versus the drain-source and gate-source voltages are investigated. The nMOS transistor ON-current is found to be two and a half times greater than that of the pMOS. In addition, the pMOS transistor shows about two orders of magnitudes smaller OFF-current with respect to nMOS, one for short channel length. The low value of I-OFF leads to lower static power, fascinating to digital applications. The BSIM4 model version 4.8 is utilized for extracting the mid-frequency model with a precision of more than 99%. An evident matching between NEGF and Berkeley Short-channel IGFET Model (BSIM) models is observed for the investigated logic.