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关键词： Inductance   Multichip modules   Silicon carbide   Copper   Conductors   MOSFET   Cooling   Double-sided cooling packages   low parasitic inductance   silicon carbide  

摘要： Higher switching speed requires power module package to have lower parasitic inductance. This article summarized three methods to realize low parasitic inductance. Based on these methods, this article proposed a novel double-sided cooling power module structure, which places the spacer under the bare die and utilizes the copper clips to realize the electrical connection between different copper layers. The proposed structure realized an interleaved power loop by utilizing copper clips and split dc terminals. Compared to the double-loop double-sided cooling power module structure, the parasitic inductance of the proposed structure can be decreased by more than 50% and that is only 1.3 nH. Besides, the dynamic current sharing properties and thermal performance of the proposed structure are also analyzed. Based on the proposed module, a module with three SiC mosfets in parallel is designed, fabricated, and tested to verify its low parasitic inductance performance. The proposed power module will contribute to achieving high power density applications.

关键词： Silicon carbide   Silicon   JFETs   Topology   Inrush current   Motors   MOSFET   motor start   power modules   semiconductor device packaging   SiC FET   solid-state circuit breaker   solid-state contactor   thyristors   wide-band-gap devices  

摘要： Solid-state contactors are an emerging solution in various load-switching applications such as direct-on-line starting of induction motors. The design challenge of solid-state motor contactors (SSMCs) comes from a high motor-starting inrush current defined in IEC 60947-4-2 standard. To overcome the limitation of conventional SSMC solutions using silicon thyristors (Si SCRs), a novel "ThyFET" topology is proposed to combine the high inrush tolerance of Si SCRs with the efficient nominal conduction of silicon carbide junction field-effect transistors. In this article, the ThyFET circuit is first analyzed with current commutation principles and switching waveform simulations. Next, the packaging design of a 1.2 kV, 12 A, three-phase, bidirectional ThyFET module is presented, which adopts a three-dimensional structure to minimize the module footprint meanwhile handling the thermal stress. The ThyFET SSMC prototype is then assembled and evaluated with IEC-standardized benchtop tests and direct-on-line motor-starting tests with a 480 V, 5.6 kW induction motor load. The test results have validated the light-load efficiency boost and the distortion reduction in the ThyFET SSMC as compared to commercial SSMC products. Finally, the outstanding inrush handling capability of the ThyFET circuit is highlighted by comparing to other hybrid Si/SiC switches in the literature.

关键词： SiC MOSFET   Device modeling   Temperature scaling   Parameter extraction   Validation  

摘要： In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.

关键词： Logic gates   Silicon carbide   MOSFET   Circuit faults   Switches   Protection   Resistance   Gate current   short-circuit protection (SCP)   silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET)  

摘要： Fast and reliable protection against short-circuit (SC) faults is critically important for the reliable operation of power devices. In this letter, an ultrafast and universal short-circuit protection (SCP) method is proposed for silicon carbide metal-oxide-semiconductor field-effect transistors based on gate current detection. This method exploits the characteristic of the gate current to become negative during SC faults and constant positive during normal operation. The proposed gate current detection approach swiftly identifies faults during the SC process, ensuring rapid response time. In addition, this method boasts broad applicability, being effective for both hard switching faults (HSFs) and faults under loads (FULs), and no extra auxiliary design is required for the three-pin device. The efficacy of the proposed SCP technique is validated through the testing of the SCP circuit. Experimental results demonstrate that the proposed circuit is applicable to both HSFs and FULs, with response delays of 69 ns for HSFs and 50 ns for FULs, and total protection trigger time of 383 ns for HSFs and 352 ns for FULs.

关键词： Capacitors   Switches   MOSFET   Discharges (electric)   Clamps   Silicon carbide   Voltage   Clamping   high power   power module   series-connection   silicon carbide (SiC) mosfet   voltage source converter (VSC)  

摘要： This letter employs active clamping modules (ACMs) to balance voltages of series-connected silicon carbide (SiC) mosfets in a voltage source converter (VSC). Under high power conditions, the ACM capacitors have large voltage ripples exceeding the voltage rating of SiC mosfets. It analyses the charging mechanisms in VSCs, and shows the large ripple is mainly caused by the excessive charging during the switching commutation process. Then, a control strategy is proposed to recycle this commutation energy back to the dc bus in each switching cycle. The effectiveness of this approach is demonstrated with a 7.2 kV/75A power module comprising six SiC mosfets, achieving a 70% reduction in voltage ripple during a 1.5 kV/50A test. With the proposed control strategy, the voltage ripple is independent of load conditions, and balancing of series-connected SiC mosfets and low power losses of the balancing circuits are maintained.

关键词： MOSFET   Mathematical models   Frequency modulation   Optimization   Voltage control   Steady-state   Switches   Control variable optimization   electric vehicle (EV)   generalized harmonic approximation (GHA)   phase-shift and duty-ratio (PSDR) control   three-port resonant converter (TPRC)   triple active bridge  

摘要： Isolated three-port dc-dc converters (TPCs) facilitate integration of three voltage sources/loads in electric vehicle applications. Three-port resonant converter (TPRC) is an attractive TPC topology as it inherits the advantages of resonant converters. Phase-shift (PS) control applied to TPRCs enables independent power flow control among all ports. Phase-shift and duty-ratio (PSDR) control introduces three additional degrees of freedom providing the potential for improving the converter efficiency compared to PS control. This article presents a generalized harmonic approximation-based steady-state mathematical model for a TPRC with five-variable PSDR control. Mathematical solutions to the steady-state converter bridge voltages and the ac currents under PSDR control are provided. The proposed mathematical model is integrated with a TPRC power loss model and together are used to formulate a control optimization problem for evaluating the optimal control variables at maximum converter efficiency. The optimized five-variable PSDR control is compared against PS control using a 6 kW/100 kHz rated hardware demonstrator, with efficiency improvements as high as 12.4%.

关键词： Integrated circuit modeling   Semiconductor device modeling   Analytical models   MOSFET   Circuits   Transistors   Power demand   MOSFET non-linearity model   differential pair non-linearity   charge-based   EKV model   drain voltage induced non-linearity   OTA non-linearity   amplifier non-linearity  

摘要： Energy efficiency is of utmost importance in modern applications. Power consumption optimisation could be improved by a comprehensive analytical modeling of the characteristics of critical blocks in a system. Dynamic range (DR) has a strong effect on the power consumption of analog circuits, and is determined by circuit non-linearity and noise level. Noise is well modelled even in deep sub-micron technologies, yet there is a lack of analysis and modeling of the non-linearity. An analytical MOSFET differential pair non-linearity model is presented in this work. The proposed model is universal to a wide range of technologies from long to ultra-deep sub-micron devices, and is valid for all operating regions as it is based on the EKV MOSFET model. Furthermore, a model including drain-voltage-induced non-linearity is also developed, and a concise 3 dB input intercept point (IIP3) formula incorporating the drain induced non-linearity in terms of the voltage gain is presented. The proposed models are validated with DC and AC simulations and measurements.

关键词： MOSFET   breakdown voltage   specific on-resistance   BCD  

摘要： For the past few decades, metal-oxide-semiconductor field-effect transistors (MOSFETs) have been the most important application in IC circuits. In certain circuit applications, the breakdown voltage and specific on-resistance serve as key electrical parameters. This article introduces a readily accessible approach to enhance the source-drain breakdown voltage (BVDS) of MOSFETs based on the Bipolar-CMOS-DMOS (BCD) platform without extra costs. By attentively refining the process steps and intricacies of the doping procedures, the breakdown voltages of NMOS and PMOS experienced increments of 3.4 V and 4.6 V, translating to enhancements of 31.5% and 50.3%. Parallel simulations offer insightful mechanistic explanations through simulation tools, facilitating superior outcomes. This initiative lays significant groundwork for the advancement of a comprehensive BCD process development framework.

关键词： Iron   Indium gallium arsenide   TFETs   Capacitors   MOSFET   Logic gates   Hafnium oxide   Ferroelectric (FE) FET   Hf0.5Zr0.5O2(HZO)   InGaAs   metal-ferroelectric-metal-insulator-semiconductor (MFMIS)   tunnel FET  

摘要： We study device structures and their design points of HfZrO X -based InGaAs metal-ferroelectric-metal-insulator-semiconductor (MFMIS) ferroelectric tunnel FETs (Fe-TFETs) based on ferroelectric (FE) polarization-controlled band-to-band tunneling (BTBT) for stable nonvolatile memory (NVM) operation. We monolithically integrated a HfZrO X MFM capacitor into the baseline tunnel field-effect transistor (TFET), which has steep subthreshold swing (SS) characteristics of sub-60 mV/decade with a HfO2 /Al2O3 gate-stack, compared to the reference MOSFET. We found temperature-stable NVM behaviors of the InGaAs Fe-TFET compared to the InGaAs ferroelectric MOSFETs (Fe-MOSFETs) at the measurement temperature range from - 20 C-degrees to 85 C-degrees. Furthermore, we explored the scaling effects of the MFMIS structure using a high- kappa HfO2 gate insulator layer to pursue a steep SS, and a large capacitance ratio between the dielectric (DE) and FE capacitors. The InGaAs MFMIS-structure Fe-TFET achieves stable retention over 10(4) s and excellent endurance during 10 6 cycles at the DE/FE capacitance ratio of 27.5.

关键词： Normally-off   GaN MOSFET   Enhancement-mode (E-mode)   Selective regrowth technique (SRT)   Selective area regrowth (SAG)   And AlGaN  

摘要： A normally-off GaN MOSFET is successfully fabricated by using the selective regrowth technique (SRT) with regrown AlGaN layer on source/drain (S/D) region. The GaN MOSFET with regrown AlGaN layer and Lg of 10 mu m shows enhanced electrical performance such as maximum drain current (ID,max) of 57 mA/mm, maximum transconductance (gm,max) of 11 mS/mm, and field-effect mobility (mu FE) of 59 cm2/V & sdot;s, respectively, compared to the GaN MOSFET with n+-GaN selective regrowth in S/D region. This is because of the high 2DEG density formed by AlGaN/GaN heterojunction in S/D region. Moreover, to accommodate the poor structural quality of the narrow region regrowth of AlGaN layer on the S/D region, wide regrown AlGaN layer is applied to the GaN MOSFET. Especially, the off-state breakdown voltage improves from 25 V to 192 V with the improved structural quality of wide regrown AlGaN layer and optimized structure and the application of the 70-nm thick SiO2 passivation. These result shows that GaN MOSFET with wide regrown AlGaN layer on S/D region is beneficial to achieving high-quality and uniform normally-off GaN MOSFETs with excellent electrical performance.