课程文献中心 更多>>

关键词： Temperature measurement   Sensors   MOSFET   Current measurement   Transient analysis   Temperature sensors   Silicon carbide   Calibration   silicon carbide   thermal characterization   thermal impedance   thermal transient measurement  

摘要： This paper aims to provide a guideline with respect to a reproducible thermal transient measurement for SiC MOSFETs. Although the thermal transient measurement based on source-drain voltage is a widely applied method for characterizing the thermal properties of MOSFETs, the approach developed for silicon-based devices may not be directly applicable to SiC devices. Therefore, this paper investigates the thermal transient measurement method for SiC MOSFETs using the source-drain voltage as the temperature-sensitive electrical parameter. A comprehensive investigation of its linearity, sensitivity, and stability toward yielding the thermal structure-property of the device has been carried out. The investigation includes two primary characterization procedures: temperature calibration and cooling curve measurement. The associated key testing conditions, such as gate voltages, sensing and heating currents, etc., are covered. The study examines the impact of these conditions on both static and dynamic performance to provide a better understanding of the reproducible thermal transient measurement for SiC MOSFETs. The evaluation is also validated by different devices, including four SiC MOSFETs with different vendors, voltages, and currents.

关键词： Latches   Transistors   SRAM cells   Reliability   MOSFET   Reliability engineering   Ions   High robustness   low cost   polarity hardening technology   quadruple-node-upset (QNU)   radiation hardening   source-isolation technology  

摘要： This article proposes an exceptionally reliable and low-cost quadruple node upset tolerant latch (L C-QNUTL)suitable for the 65 nm CMOS technology. The innovative L C-QNUTL latch is primarily composed of three soft-error-immune(SEI) static random-access memory (SRAM) cells and a triple-level C-element (CE) unit, which includes five two-input CE and a clock-gating (CG)-based two-input CE. The SEI SRAM cell utilizes polarity hardening technology and source-isolation technology, significantly reducing the number of sensitive nodes and enhancing the latch's stability. By using the high-speed transmission gate (TG) technology and stacked structures, the proposed latch offers minimal overhead in terms of delay and power consumption, yielding an improved power delay area product (PDAP). When compared to contemporary quadruple node up set (QNU)-tolerant latch designs (including HLMR, 4NUHL,and LDAVPM), the new design offers substantial improvements-29.53% less delay, 80.09% reduced power consumption, 58.52%smaller silicon area, and 433.43% improved comprehensive PDAP on average. Furthermore, simulation results demonstrate that the L C-QNUTL latch exhibits reduced sensitivity to process, voltage, and temperature (PVT) variations, thus providing superior reliability, which makes it an ideal choice for safety-critical applications.

关键词： Discrete power electronics   SiC MOSFETs   Solder joint degradation   Active power cycling   Thermal resistance   Finite element analysis  

摘要： The development of innovative power electronics solutions for automotive applications introduces new reliability requirements for electronic assemblies and interconnection technologies. Many of the reliability methods used in power electronics require extensive experimental data, resulting in long product design cycles. This work focuses on developing a simulation-driven approach to assess the solder joint reliability of a discrete silicon carbide MOSFET by monitoring its degradation under power cycling in the thermal and thermo-mechanical domains using the thermal resistance of the stack as a failure metric. Active power cycling tests are performed to determine the loading condition at which end-of-life is reached due to a 20 % increase in thermal resistance. Numerical analysis using finite element simulations is conducted to gain a physical understanding of the failure criterion, allowing to monitor solder degradation based on the thermal resistance and to pinpoint failure at individual interconnects within a solder bump array. The proposed methodology aims to accelerate the assurance and of discrete electronic devices.

关键词： Silicon carbide metal oxide semiconductor transistor   Discrete components   High-frequency drive   Crosstalk   Low loss  

摘要： To reduce the loss of the high-frequency drive circuit of silicon carbide metal oxide semiconductor transistor (SiC MOSFET) and to better utilize the performance of the SiC MOSFET, a high-frequency drive circuit based on discrete components (DC-RGD) is proposed in this paper. The inductance is added to provide a low-impedance circuit for the gate charge/discharge circuit of the SiC MOSFET, enhancing the circuit's immunity to interference. At the same time, an auxiliary switching tube is added to form an active clamping circuit to reduce the impact of parasitic parameters on the drive waveform in high-frequency applications. A negative voltage is generated by adding a series capacitor to the drive circuit, ensuring the auxiliary switch is on during SiC MOSFET turn-off. This switch is not driven by an additional drive circuit, thus simplifying the circuit. The operation and losses of the circuit are analyzed, and the design methodology of the circuit is given. Finally, a Boost converter with an input of 24 V and an output of 48 V/5 A is constructed. The operating waveforms at a frequency of 0.5 MHz are tested, and the loss of the driving circuit is only 0.317 W. The results show that the proposed driving circuit ensures the reliability of the SiC MOSFETs and is able to solve the problem of the driving waveform oscillations efficiently, with a better anti-interference capability and lower loss.

关键词： Switches   Inductance   MOSFET   Voltage   Silicon   Insulated gate bipolar transistors   Schottky diodes   Current source inverter   current switch   DC-AC converter   design   half-bridge   loop-inductance   module   packaging   reverse-voltage blocking switch   three-phase inverter   CS   CSI   HB   RVB  

摘要： Wide-band gap (WBG) devices have enabled the re-emergence of current source inverters (CSIs). With increased dv/dt and di/dt of WBG devices, the parasitic inductances in the power loop and gate loop are critical in reducing the induced voltage at the devices. This paper presents the design consideration and development of a low inductance 3.3 kV silicon carbide (SiC) based reverse voltage blocking (RVB) half-bridge (HB) module for CSI-based applications. The module comprises a SiC-MOSFET (3.3 kV/50 A die) and a SiC-MPS diode (3.3 kV/50 A die) to form a 3.3 kV SiC-based RVB switch in the HB configuration. The module inductance is estimated using ANSYS Q3D. The impact of the unequal busbar parasitic inductances between the CSI phases on the RVB switch in the HB module is discussed considering the medium voltage (MV) dv/dt and di/dt limits. The increased substrate thickness helps reduce the module's parasitic capacitance and thus reduces electromagnetic interference (EMI) concerns. The static and dynamic characterization of the RVB switch or current switch (CS) is performed to demonstrate the functionality of the proposed module. The static and dynamic characterization is used to understand a three-phase CSI system's switching frequency limits, heat sink, and cooling requirements. The steady-state hardware result and the dynamic response of the three-phase CSI with the proposed module are presented.

关键词： 高温超导性  

ISBN: (纸本)9787030786883

摘要： 本书共8章。第1章介绍滤波器的发展史, 着重分析射频滤波器的种类及体声波滤波器的研发进展。第2章和第3章从体声波滤波器的物理基础出发, 基于声波的传输理论与材料的压电理论推导出器件仿真模型, 并以两款体声波滤波器的设计案例介绍设计方法的应用, 展现关键影响因素在设计过程中的调整规律。第4-6章依次介绍了AIN薄膜的制备与表征方法、体声波滤波器的关键制备工艺与封装技术, 结合本书作者团队的研究成果, 表明了单晶AlN体声波滤波器 (SABAR) 技术路线较多晶AIN路线的优势。第7章着重介绍体声波滤波器在民用通信、国防、传感及医学领域的应用。第8章分析与展望了体声波滤波器的前沿技术。

关键词： Degradation mechanism   Fowler-Nordheim (FN) localization method   inrush current   metal-oxide-semiconductor-field-effect transistor (MOSFET)   silicon carbide  

摘要： In this letter, an inrush current degradation mechanism of trench gate inside silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistor (Mosfet) is investigated in depth under different turn-off V-GS. The preconditioning is introduced to guarantee the accuracy of gate-related parameters, avoiding effect from recoverable components. Meanwhile, a new Fowler-Nordheim localization method is proposed to nondestructively evaluate degradation extent of gate oxide on channel and nonchannel region by achieving barrier height phi(B) of hole and electron, respectively. The degradation mechanism is the substantial hole injection into gate oxide on channel region due to the electric field direction and high hole density resulting from negative V-GS and inrush current, respectively. The degradation mechanism provides significant physical insights to better understand the impact of different turn-off V-GS and safely use SiC mosfet in practical circuits. The proposed methodology also provides novel general guidance for nondestructively, assessing the quality of gate oxide of channel and nonchannel region under various operation conditions.

关键词： double-gate   surrounding-gate   MOSFET   SPICE   surface potential   PSP  

摘要： We introduce a compact core model for double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs designed for circuit simulations. Despite its high precision, the model is crafted to retain the same analytic formulation of the industry standard Pennsylvania State and Philips (PSP). Instead of linearizing the drain current as in the PSP model, we employ a quadratic symmetric polynomial interpolation of the charge in the channel. This eliminates the need for cumbersome derivatives, simplifications, and intricate coding when integrating into a circuit simulator, thereby preventing singularities during numerical iterations. Moreover, thanks to its mathematical formulation equivalent to PSP, this model simplifies the coding of terminal charges, capacitances, potentials, and electric fields in the channel within circuit simulators. We validate the accuracy of the model through comparisons with numerical solutions and experiments from the literature.

关键词： Hydrogen sensor   P -type MOSFET   MoTe 2   NEGF   Charge plasma -based electrodes   Sensing performance  

摘要： The paper presents a novel P -type molybdenum ditelluride (MoTe 2 ) Metal -OxideSemiconductor Field -Effect Transistor (MOSFET) designed for high sensitivity hydrogen sensing applications. Through the utilization of palladium at the source -drain charge plasma electrode, P + regions at both ends are generated, obviating the necessity for low -dimensional MoTe 2 doping. Simultaneously, the inclusion of palladium on both regions act as the sensing area, resulting in notably heightened sensitivity. The study employs Non -Equilibrium Green ' s Function (NEGF) formalism to investigate the carrier transport properties of the device. The results provide valuable insights into less explored area of p -type MOSFET performance as Hydrogen(H 2 ) gas sensor and its potential.

关键词： JFETs   MOSFET   Resistance   Silicon carbide   Optimization   Particle swarm optimization   Threshold voltage   SiC   MOSFETs   multi-objective optimization   particle swarm optimization  

摘要： This work employed the particle swarm optimization (PSO) algorithm to assess the trade-off between breakdown voltage (BV) and on-state resistance (RDS,on) in 4H-SiC metal oxide semiconductor field effect transistors (MOSFET) for power devices. In this work, the numerical model obtained after analyzing the resistance composition is utilized as the objective function in PSO to determine characteristic parameters in double-diffused metal oxide semiconductor field effect transistors (DMOSFET). These equations are input for the PSO algorithm. The derived characteristic parameters include the drift region doping concentration and thickness, cell size, channel length, JFET region length, JFET region thickness, and doping concentration. To adhere to common application constraints, this work optimizes these characteristic parameters to minimize the R-DS, (on) under typical BV ranging from 100 to 2000 V. The R-DS, (on) for some typical applications was extracted and validated through TCAD simulations to ensure algorithm accuracy. The reported results confirm that PSO yields superior outcomes and may be considered when designing devices. This work offers helpful insights into the design of characteristic parameters for 4H-SiC power DMOSFET devices and evaluates the feasibility of using PSO to optimize the characteristic parameters of power devices.