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关键词： power MOSFET   temperature measurement  

摘要： In order for full utilization of the switching devices and safe continued operation of the power converter at the same time, the junction temperature of the switching devices needs to be accurately monitored without shutting down the motor drive. This paper derives an analytical junction temperature calculation method by using Laplace transformation and thermal network theory. Based on an actual motor drive, a simulation model is established using platform for power electronic systems (PLECS). Through comparison, the derived method is proven to be able to calculate junction temperature accurately. Accurately monitoring the junction temperature online is essential for the safety of the switching devices, the full utilization of their capacity and the safe continued operation of the power converter. This paper derives an analytical junction temperature calculation method based on Ohm's law of thermal network and the Laplace transform. By comparing the PLECS simulation results, the validity and accuracy of the derived method are verified. image

关键词： MOSFET   THD   SPWM   inverter   delay   signal correction  

摘要： In the inverter circuit, the speed at which the MOSFET is impacted by the presence of a parasitic inductor within the printed circuit board (PCB) leads to a delay in the switching process. Furthermore, the parasitic inductor within the circuit can easily form an LC oscillation with the parasitic capacitor of the MOSFET. These two issues result in an inconsistency between the actual output of the MOSFET and the driving signal waveform, leading to distortion in the sinusoidal pulse width modulation (SPWM) waveform and an increase in total harmonic distortion (THD). It is a common practice to mitigate gate oscillation by introducing a resistor at the gate of the MOSFET. However, elevating the resistance leads to deceleration in the charging process of the MOSFET's parasitic capacitor, consequently causing an increase in the switching delay, and thereby increasing THD. Therefore, an effective strategy to reduce THD is proposed in this paper, while augmenting the gate resistance, computing the MOSFET switching delay, and applying corrective compensation. In this way, the inherent issues of the switch are addressed, resulting in inverter output waveforms that closely resemble sine waves and reduced THD. Through a combination of simulation and empirical experimentation, the efficacy of the proposed approach in significantly reducing THD in the inverter's output waveform has been empirically substantiated.

关键词： MOSFET devices  

摘要： SiC double trench MOSFETs have the advantage of generating a deep P+ layers through the trench source, effectively mitigating electric field crowding at the bottom edge of the gate oxide. However, the depletion region induced by the deep P+ layers narrows the current path between the gate and P+, resulting in an increase in the on-resistance. In this study, we addressed this problem by introducing CSLs through ion implantation in the 1.2 kV SiC double trench MOSFETs. CSL concentration optimization resulted in a 3.92 % decrease in on-resistance and a 3.19 % increase in the figure of merit. Therefore, the SiC double trench MOSFET with optimized CSL concentration has improved on-resistance characteristics and figure of merit compared to the conventional structure. © The Korean Institute of Electrical Engineers.

关键词： Temperature sensors   Sensors   Temperature measurement   MOSFET   Subthreshold current   Calibration   Sensitivity   Temperature sensor   current ratio of two subthreshold MOSFETs   one-point calibration   high accuracy  

摘要： Modern high-performance processing chips utilize on-chip temperature sensors to monitor the temperature. In addition to a small area and low power, there is a strong demand for high accuracy with low-cost calibration. This brief presents an accurate sensor that converts the thermal information contained in the current ratio of two subthreshold MOSFETs to duty cycle. The proportional operation ensures that the slope of the linear sensing relationship remains unaffected by process variation, thereby guaranteeing the achievement of one-point trimming. The dynamic slope compensation (DSC) method is proposed to improve sensor supply sensitivity. Implemented in a 0.153- mu m CMOS process, the proposed sensor occupies only 1632 mu m(2) and consumes 0.7 mu W at room temperature. The measured inaccuracy is +1.2/ -1.0(degrees)C ( 3 sigma ) in -20(degrees)C similar to 120(degrees)C after one-point calibration and systematic error removal. With the assistance of DSC, the sensor can achieve a supply sensitivity of 4.3 degrees C/V.

关键词： Resonant converters   RLC circuits   MOSFET   Zero voltage switching   Resonant frequency   Frequency conversion   Rectifiers   Current sharing control   interleaved   LLC resonant converter   PWM   zero-voltage switching (ZVS)  

摘要： Due to the particular advantages of the LLC resonant converter (e.g., high-efficiency and high-power density), it has been widely applied in both energy and power areas. The interleaved parallel structure LLC resonant converter can reduce the output ripple of a single LLC resonant converter and improve the upper limit of power capacity. However, there always exist parameters deviation between the parallel modules. As a result, the interleaved paralleled LLC resonant converter inevitably experiences power imbalance in each transmission circuit. To solve the problem, a new current-sharing control method is proposed in this work. The proposed method takes the conditions required for zero-voltage switching (ZVS) soft-switching characteristics of LLC resonant converters into consideration and adjusts the duty cycle of driving signals of two interleaving parallel LLC resonant converters independently, further realizes the power equalization of two-phase resonant converters. Extensive simulations and measurements are performed. It is found that the current sharing control method can reduce the current imbalance from more than 20% to less than 3% when the resonant inductance of the two interleaved LLC resonant converter deviates by 6.4% and the resonant capacitance deviates by 9.1%.

关键词： Breakdown voltage   split-stepped field plate   gallium oxide   power figure-of-merit   high power   high frequency  

摘要： A split-stepped gate field plate design has been incorporated on a gallium oxide (Ga2O3) metal-oxide semiconductor field-effect transistor (MOSFET). The aim of the present work is to unfold the potential of Ga2O3 MOSFET by enhancing its breakdown limits and also to overcome the challenge of simultaneous improvement in power as well as radio frequency (RF) metrics. An extensive simulation study focusing on analog and RF metrics has been carried out using technology computer-aided design simulations of the proposed device in a calibrated environment, and a comparative analysis of split stepped gate field plate design, shorted stepped gate field plate design, and conventional Ga2O3 MOSFET design has also been performed. The results highlight the superiority of the proposed device, and a substantial enhancement in breakdown voltage (i.e., 106.36% relative increase) and power figure-of-merit (i.e., 282.70% relative increase) has been demonstrated.

关键词： crosstalk suppression   gate drive   impedance regulator   reverse turn-off   SiC MOSFET  

摘要： For high-frequency switching applications, silicon carbide (SiC) devices are more suitable than silicon-based devices, which is conducive to improving the efficiency and power density of power electronic equipment. However, as the switching frequency increases, the influence of parasitic parameters on the switching characteristics of devices becomes increasingly apparent. When SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are applied in bridge circuits, the crosstalk problem easily occurs with the complementary conduction of upper and lower transistors, which seriously limits the promotion of SiC MOSFETs. However, the existing crosstalk suppression drive circuit tends to increase the switching loss, switching delay, and control complexity;therefore, a gate drive with crosstalk suppression capability is proposed. In this paper, the gate drive has two features: a negative voltage to shut down the SiC MOSFET;and an adjustment of the gate-source equivalent impedance. To accomplish this goal, the mechanism of crosstalk voltage generation is analyzed. Furthermore, the operation principle of the gate drive is analyzed, and the parameters of the gate drive are designed. Eventually, the proposed gate drive is verified by an LTspice simulation and experimental platform. The results prove that the gate drive can suppress the crosstalk voltage without affecting the switching speed.

关键词： Silicon carbide   MOSFET   Schottky diodes   Degradation   Ions   Radiation effects   Breakdown voltage   Charge-balanced (CB) power devices   degradation   heavy ion   junction-barrier Schottky (JBS) diodes   metal-oxide-semiconductor field-effect transistor (MOSFET)   silicon carbide (SiC)   single-event burnout (SEB)   single-event effects (SEEs)   single-event leakage current (SELC)   superjunction devices  

摘要： Experimental heavy-ion responses of 3-kV charge-balanced (CB) SiC power devices are compared with those of 3.3-kV planar SiC devices. The devices are similar, except the epitaxial region of the CB devices is heavily doped compared with the planar devices. The higher doping in the epitaxial region results in loweron-resistance, but typically leads to a lower threshold drain voltage at which single-event burnout (SEB) occurs. The experimental results demonstrate, however, that the CB devices have a similar SEB threshold to the planar devices due to the improved electric field distribution.

关键词： Oxide semiconductors  

摘要： This article introduces a comparative study of the losses in Voltage Source Inverter (VSI) based on Metal-Oxide- Semiconductor Field-Effect Transistors (MOSFETs) depending on whether or not the latter are associated with antiparallel diodes. These diodes are optional because MOSFETs have an intrinsic diode capable of conducting reverse currents when their channel is in OFF state. However, it induces additional reverse recovery losses and damaging voltage overshoots. This undesired circumstance occurs during the mandatory switching cell dead-time and is accurately modelled and assessed in this study. Conversely, Schottky diodes feature almost zero reverse recovery losses. Hence, combining each MOSFET with an antiparallel Schottky diode may reduce the converter overall losses. To assess this strategy, an analytical model of the charge stored within the body diode is developed and then compared to experiments using the Double Pulse Test (DPT). It reveals accurate and well suited because it requires only two constant macro parameters which permits to forecast the reverse recovery losses over a wide range of operating conditions, namely switched current, current slope and dead time duration. The selected model is applied in the case where a Schottky diode is placed antiparallel to the MOSFET. It then appears clearly that the interest of such a combination depends on the static characteristics of both the MOSFET and the Schottky diode. This output is a noteworthy point for power electronics designers. Finally, the developed model is applied in the standard use case of the Voltage Source Inverter (VSI). The results reveal the advantage of the suggested model in this use case because the current evolves significantly over time. The outcome of this VSI analysis shows that a significant recovery losses decrease is achieved with good sizing fit between the MOSFET transistor and the additional Schottky diode. © 2024 The Author(s)

关键词： Die top system (DTS)   failure mechanism   Kelvin source   multichip power module   power cycling   SiC MOSFET  

摘要： Because of the wide application of die top interconnects with Cu bonding wire, the weak points in SiC MOSFET power modules presented a huge difference compared to the conventional modules with Al wire. The lack of understanding of the failure modes and mechanisms has become an obstacle to improving its reliability further. In this article, the accelerated aging of the SiC MOSFET power module using die top system (DTS) was carried out using a power cycling test (PCT). The delamination of the upper sintered Ag layer became the primary failure mode. The Al wire of the Kelvin source was also found burned out. It was verified that imbalanced electric and thermal distribution in different power branches of the multichip paralleled module gradually deteriorated during power cycling by the electrothermal coupling finite element simulation and circuit analysis. Then, the burning of the Kelvin source bonding wires was due to the large circulating current flowing through the Kelvin source bonding wires across different branches. In addition, the chip level degradation of SiC MOSFETs resulting from the package degradation was found. The heat concentration caused the broken interlayer dielectric (ILD) due to the large current flowing through the tail region of the gate bus horizontally.