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关键词： MOSFET   Logic gates   Schottky diodes   Electrons   Silicon carbide   Current density   Leakage currents   Voltage   Switching loss   Materials reliability   ATMOS   specific on resistance   body diode   reverse blocking leakage current   reverse cut-in voltage   switching loss  

摘要： A novel Asymmetric Trench SiC MOSFET (ATMOS) with Integrated Three Channels (ITC) is presented, which improves the performance and reliability significantly. The ITC includes the reverse conduction channel (Ch3) and double forward conduction channels (Ch1 and Ch2). The Ch3 is constituted by the Self-Biased MOSFET (SBM), forming a low barrier due to the drain-induced barrier lowering effect, which results in a lower turn on voltage compared with the p-i-n body diode. On the other hand, the Ch1 and Ch2 are constituted by the side trench MOSFET and additional bottom planar MOSFET, respectively. It shortens the width of the JFET region, and a lower gate oxide electric field is achieved. The reverse blocking leakage current (IBL) caused by the drain-induced barrier lowering is suppressed. Moreover, the bottom planar MOSFET reduces the gate-drain charge (QGD) and switching losses due to the reduced coupling area between the Gate and Drain. Finally, The Ch1 and Ch2 provide double electron current paths during forward concoction, which reduces the specific on-resistance (Ron,sp) of the device remarkably. The simulation results show that the proposed ITC-ATMOS achieves a reduction ${\mathrm { V}}_{\mathrm { cut-in}}$ of the body diode from 2.8V to 2.0V at 50A. The peak electric field ${\mathrm { E}}_{\mathrm { max}}$ is reduced to 1.27MV, and the leakage current(IBL) caused by the integrated SBM (I ${_{\text {BL}}} {=} 10{<^>{-}7 }$ A) is much smaller than integrated Schottky Barrier Diodes (SBD) (I ${_{\text {BL}}} {=} 10{<^>{-}5 }$ A) for blocking characteristics at high-temperature, thus long-term reliability is greatly enhanced. Moreover, a decrease in ${\mathrm { R}}_{\mathrm { on,sp}}$ of 28.57%, and reductions in ${\mathrm { Q}}_{\mathrm { GD}}$ and switching losses by 20.60% and 41.4% are achieved when compared with the Conventional ATMOS, respectively.

关键词： TFET-MOSFET hybrid SRAM   Forward p-i-n current   Static power consumption   Multiplexing strategy   Read/write speed  

摘要： Due to the limitation of MOSFET subthreshold swing, traditional MOSFET-based static random-access memory (SRAM) circuits are difficult to meet the design requirements of low-power integrated circuits. To address these issues, we proposed a half-select disturb-free 12T TFET-MOSFET hybrid SRAM bitcell. It can avoid the forward pi-n current and effectively mitigate the effect of current degradation, which greatly reduces the static power consumption of the circuit and improves the performance of SRAM. Specifically, compared to 12T, the write delay of the hybrid bitcell decreased by approximately 13.994 % at 0.6 V. Meanwhile, a TFET-MOSFET hybrid 8T SRAM array is proposed by a multiplexing strategy to reduce the area consumption. The proposed 4 x 4 hybrid SRAM array is comparable to the 12T bitcell in terms of static noise margin (SNM), read/write speed, and static power consumption. These results indicate that the proposed TFET-MOSFET hybrid 8T SRAM array is a good choice for applications that require low power consumption and high stability.

关键词： Pulse transformers   Tumors   Voltage   MOSFET   Inductance   Topology   Generators   Damping   Windings   High frequency   Drive circuit   high-frequency bipolar pulses (HFBPs)   irreversible electroporation (IRE)   magnetic isolated   pulse transformer   undershoot  

摘要： High-frequency irreversible electroporation (H-FIRE), which employs high-frequency bipolar pulses (HFBPs) with high voltage has been successfully used for tumor ablation with the inhibition of muscle contraction. This article designs an undershoot damping circuit with magnetic isolation drive embedded (MI-UD) in main topology of step-up transformers to reduce the undershoot voltage resulting from the energy release of excitation inductance and improve the pulse frequency when outputting HFBPs. The proposed main circuit topology could generate HFBPs with one magnetic core, and no additional magnetic core reset circuit is needed for the excitation inductance. Moreover, the designed drive circuit only needs two control signals with delayed turn-off, including the controls of the MI-UD circuit. Theoretical analysis, simulation, and experimental test indicate that three modules of step-up pulse transformer could output HFBPs. The pulse amplitude could reach +/- 3 kV with the voltage gain of 11.1 (ratio of 1:4, three modules) and dc supply of 270 V. The pulsewidth ranges from 300 ns to 2 mu s. A total energized time of 100 mu s within the burst can be achieved to meet the H-FIRE treatment. The maximum frequency is 400 kHz within the burst. The undershoot at 2 mu s and +/- 3 kV is only 3.3%.

关键词： SiC MOSFET   Modelling   Physical effects   Power electronic  

摘要： An improved semi-physical model for a SiC MOSFET incorporated with relevant physical effects and temperature characteristics is proposed based on the EKV model. A simulation analysis of the Junction Field Effect Transistor (JFET) effect, Drain Induced Barrier Lowering (DIBL) effect, channel length modulation effect, velocity saturation effect, and interface trap charge effect in SiC MOSFET devices is performed using Sentaurus TCAD. Based on the influence of physical effects on the characteristics of SiC MOSFET devices, mathematical corrections r(V-gs) and r(V-ds), which can describe the relevant physical effects, are introduced into the original EKV model. The capacitance is accurately modelled to achieve the required match between the transient characteristics of the devices. The accuracy of the model is verified by static tests and double-pulse experiments. Results show that the improved model can do a better job of simulating the actual operating conditions of the device. In addition, its accuracy and applicability are greatly improved, providing a semi-physical model with a wider range of applicability for the simulation of SiC MOSFETs in power electronic systems.

关键词： Circuit faults   Logic gates   Field programmable gate arrays   Leakage currents   X-ray lasers   Materials reliability   Transistors   Electron traps   Semiconductor lasers   MOSFET   X-Ray   leakage   DPA   side-channel  

摘要： Recent research demonstrates the feasibility of X-ray attacks. Unlike traditional fault injection methods, X-rays offer precise spatial targeting because of their short wavelength and high penetration power. This allows attackers to selectively target specific regions within a device, from individual transistors to larger blocks. This necessitates a new perspective on hardening techniques, requiring designers to consider the impact of X-ray irradiation on both fault injection and power consumption. To address this challenge, the paper proposes a characterization flow that analyzes the differences in side-channel leakages of FPGA components and their susceptibility to increased leakage due to X-ray effects. Despite the fundamental differences between ASIC and FPGA layouts, they both share the characteristic of being MOS technology-based, which makes them both susceptible to TID effects. The simulation results strongly support the theory that X-rays can induce leakage currents, thereby amplifying the side-channel information leakage observed in our experiments on FPGAs. Furthermore, these results provide concrete evidence that different FPGA components exhibit varying susceptibility to X-ray-induced leakage. Our findings reveal a clear hierarchy of vulnerability, with interconnects being the most susceptible elements, followed by registers, and lastly, logic components (LUTs and MUXes). This differential vulnerability offers valuable information for designers of secure cryptographic circuits. By understanding how X-rays impact different components, hardening techniques can be strategically targeted to provide the most effective protection against both fault injection and side-channel leakage.

关键词： Silicon carbide   MOSFET   Current density   Schottky diodes   Logic gates   Hands   Failure analysis   Temperature distribution   P-n junctions   Voltage measurement   Embedded SBD   failure mechanism   leakage current   short-circuit   silicon carbide (SiC) MOSFETs  

摘要： The short-circuit ruggedness and failure mechanism of a commercial silicon carbide (SiC) MOSFET with embedded Schottky barrier diode (SBD-MOS) are evaluated and revealed in this article. Compared with a conventional planar-type SiC MOSFET (C-MOS), a distinctive difference in failure phenomenon is observed for SBD-MOS under short-circuit condition. When the short-circuit withstanding time ( $\textit{t}_{\text{sc}}$ ) of SBD-MOS exceeds 3.5 $\mu $ s at 600-V bus voltage, the device fails to shut down, even though the gate is turned off. After a brief decrease, the short-circuit current rises again and continues for a period of time, eventually leading to the destructive failure. In contrast, C-MOS does not observe a similar event and $\textit{t}_{\text{sc}}$ reaches to 6.5 $\mu $ s. The finite-element simulation and physical analysis reveal that short-circuit stress cause a severe leakage current within the embedded SBD, thereby preventing the interruption of short-circuit current. Unfortunately, the power dissipation caused by SBD leakage current provides a positive feedback with temperature, and thus, temperature continuously increases toward a higher value, eventually leading to the destructive failure of devices.

关键词： Stress   MOSFET   Electrons   Electron traps   Degradation   Logic gates   Gallium   Threshold voltage   Transient analysis   Mathematical models   Ga2O3-on-SiC (GaOSiC) MOSFET   gallium oxide   heterogeneous   instability   unipolar bias stress  

摘要： In this study, the instability of heterogeneous Ga2O3-on-SiC (GaOSiC) MOSFETs under unipolar positive/negative bias stress (UPBS/UNBS) was investigated systematically. By adjusting key parameters of stress voltage waveform, including frequency (f), holding time ( t(h) ), rising time ( t(r) ), and falling time ( t(f) ), a two-phase shift in threshold voltage ( V-T ) with cycle number ( Cn ) was observed in the UPBS measurement. The UPBS-induced positive V-T shift is primarily attributed to electron trapping by traps at/near the Al2O3/ beta -Ga2O3 interface during the t(r) transient. At the beginning of UPBS test (first phase of degradation), most trap states are unoccupied and the electron trapping is predominant, leading to similar V-T shifts in different stress conditions. With Cn further increasing (second phase of degradation), deeper level traps begin trapping electrons due to the accumulation effect, which has been found to have a strong correlation with t(f). Notably, a monotonic positive shift in V-T was also observed in the UNBS measurement. This V-T shift under UNBS was modeled using a stretched exponential equation. Parameters of this equation were used to characterize the rate and magnitude of V-T degradation under various stress conditions, elucidating the significant role of f and t(r) in the V-T degradation of GaOSiC MOSFET. TCAD simulations suggest that the monotonic positive shift in V-T under UNBS is caused by electron trapping at the beta -Ga2O3/SiC interfacial layer, which contains a high density of traps.

关键词： Zero voltage switching   Inductors   Capacitors   Voltage   Rectifiers   Power supplies   Noise   Voltage control   Switching frequency   MOSFET   Power factor correction (PFC)   totem-pole bridgeless PFC converter   triangular current mode (TCM)   zero-voltage switching (ZVS)  

摘要： In this article, a totem-pole bridgeless power factor correction converter with zero-voltage switching (ZVS) capacitor is proposed, in which, the power switches can realize ZVS over the entire line cycle and the detection of ZVS current is simplified. The operation principle of the converter is analyzed. Regarding the resonance between ZVS capacitor and the inductor, the linearization of inductor current and the parameters of the main components are analyzed in detail. The on-time of switches, the voltage of ZVS capacitor and a control scheme are provided. A 100-W prototype is built in the lab to verify the operation of the proposed converter. The measured conversion efficiency and PF are 98.15% and 0.986, 97.21% and 0.984, at 220 V/100 W and 110 V/65 W, respectively.

关键词： Writing   Silicon-on-insulator   Layout   Substrates   Random access memory   Logic gates   Junctions   Voltage   Transistors   MOSFET   3T-DRAM   1T layout   BIS-DRAM   non-destructive and in-situ reading   random access   22 nm FDSOI technology  

摘要： A novel device integrating all the functions of the three-transistor Dynamic Random Access Memory (3T-DRAM) into one-transistor (1T) layout is demonstrated with 22 nm fully depleted silicon-on-insulator (FDSOI) technology. The 1T layout is realized by the proposed bipolar junction transistor (BJT) assisted in-situ sensing DRAM (BIS-DRAM), in which the erase and program function are conducted through a BJT embedded in the substrate. The charge is stored in the buried oxide (BOX) capacitor of the SOI MOSFET and read out through the interface coupling effect, with the top gate serving as a selector for random access. This smart design enables the non-destructive and in-situ reading with low disturbance and compact layout. Experimental results demonstrate 5 ns write speed and >= 7.9 s retention time, with a minimum write voltage down to 0.2 V, showing great potential for embedded DRAM (eDRAM) applications.

关键词： Transistors   MOSFET   Electric potential   Photodiodes   Lighting   Junctions   Standards   Logic gates   Power demand   Sun   1-T pixel sensor   high integration   CMOS process-compatible   tunable responsivity  

摘要： In this work, we present a novel one-transistor active pixel sensor with enhanced strong light response based on a semi-floating gate (SFG) transistor. The proposed device employs a metal-oxide-semiconductor (MOS) capacitor to store photo-generated holes from backside illumination, resulting in a larger full well capacity and improved light absorption characteristics. Our results demonstrate that the device exhibits an exceptionally wide light intensity response range, from 1.0x10(-6) mW/cm(2) to 1.0x10(2) mW/cm(2), achieving a substantial readout current difference exceeding 0.1 mu A. Furthermore, the low light response can be enhanced by more than 8 times by adjusting the operating voltage. Under standard 0.13-mu m node, the fill factor is also improved by 30% without increase in cost and tenfold reduction is achieved in power consumption simultaneously.