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关键词： MOSFET   Gallium   Silicon carbide   Semiconductor device modeling   Logic gates   Semiconductor process modeling   Silicon   Nitrogen   Ion implantation   High-voltage techniques   Beta-phase gallium oxide (beta-Ga2O3) MOSFET   current blocking layer (CBL)   medium-voltage device   nitrogen ion implantation   power loss   temperature dependence  

摘要： The structural design, static, dynamic power losses and short-circuit (SC) robustness of vertical Ga2O3 planar gate mosfets for medium voltage (3300-6500 V) ratings are first analyzed and comparatively investigated by technology computer-aided (TCAD) simulation. The specific on-resistance of Ga2O3 planar mosfets is 5.85 m Omegacm(2) (3300 V), 14.3 m Omegacm(2) (4500 V) and 30 m Omegacm(2) (6500 V). The Baliga figure of merit of 3300 V rated Ga2O3 mosfets is up to 2.53 GW/cm(2) (R-on,R-sp = 5.85 m Omegacm(2), BV = 3840 V, E-max(gate oxide)<4.5 MV/cm). In the third quadrant, Ga2O3 planar mosfets have a higher turn-on voltage (|V-on| > 5 V) than SiC mosfets, but lower on-resistance (7.5 m Omegacm(2)). Moreover, the switching power loss of 3300 V 1000 m Omega Ga2O3 planar mosfets is almost same as that of SiC mosfets. The reverse recovery time and reverse recovery charge of the channel diode are 8.5 ns and 18 nC, respectively. Overall, Ga2O3 planar mosfets have lower conduction losses and promising switching losses. However, its SC robustness is weaker than that of SiC. The main reason for this is the low thermal conductivity and lattice heat capacity. These findings provide meaningful references for vertical Ga2O3 planar gate mosfet deployment in future application scenarios.

关键词： Computational modeling   Mathematical models   Integrated circuit modeling   SPICE   Convergence   Software   Adaptation models   Silicon carbide   Computational efficiency   MOSFET   Circuit simulation   silicon carbide (SiC)   spice modeling   wide bandgap (WBG) semiconductors  

摘要： The recent adaptation of wide bandgap (WBG) semiconductors pushes the SPICE circuit simulation software to the very edge, requiring computationally light and accurate assessment of rapid and oscillatory transients. One of the main limitations in SPICE modeling of WBG semiconductors is the lack of built-in models in the available software, forcing usage of behavioral modeling with heavily nonlinear equations. Using such implementation leads to high computational costs and convergence issues. This work presents a general approach to the approximate modeling of WBG semiconductors, leveraging the functionality of modern open-source SPICE software to improve convergence by decoupling nonlinear model formulation from the SPICE model formulation and to move the computational cost of nonlinear model updates outside the SPICE software. The proposed modeling approach is suitable for further acceleration by FPGA implementation and machine learning surrogate modeling. To investigate the accuracy of the approximate modeling, the approximations are derived for charge and channel equations of two silicon carbide mosfets and compared in a double pulse test against the original simulation model and experimental results. It is shown that the approximate implementation maintains the accuracy of the original model in the transient simulation and improves the convergence, leading up to 59% acceleration.

关键词： SiC MOSFET   Floating field rings   Breakdown voltage   Humidity   Lithographic error  

摘要： Prior designs of the number and spacing of the Floating Field Rings (FFRs) in the edge termination of SiC MOSFETs have limitations. They neglect the possible degradation of the breakdown voltage, VBR, due to two reasons: (1) widening, alpha, of the ring due to lateral straggle of dopants during implant-action, and over-etching of the window during the prior lithography step;(2) presence of a negative SiC/SiO2 interface charge, QH, over a part or whole of the edge termination length due to migration of aluminates formed from reaction of the gate metal with humidity in the environment. We propose an improved algorithm to design a FFR structure considering alpha. Further, we show that by extending this structure by its mirrored version, we get what we call a Mirrored FFR (MFFR) structure, which is tolerant to QH as well as alpha. The concept is illustrated using well calibrated TCAD simulations of a 600 V SiC MOSFET with alpha = 0.3 mu m and QH =-3 x 1012 cm-2;the VBR with prior FFR designs degraded by up to 48 % while that with MFFR design by just 16 %. Thus, MFFR structure yields a device with the least overhead factor of VBR, that in turn allows realization of a lower specific on-resistance.

关键词： Silicon carbide   Logic gates   Switches   Delays   Control systems   Multichip modules   MOSFET   Active gate driver (AGD)   current sharing   paralleled power modules   silicon carbide (SiC)   switching gate resistance  

摘要： To ensure balanced current sharing between paralleled power modules, active gate drivers (AGDs) can be used to adjust the currents dynamically. However, achieving effective, flexible and accurate dynamic current adjustment is a challenge for AGDs under the very fast switching speed of silicon carbide (SiC) devices, e.g., <100 ns. Therefore, an online unified turn-ON/OFF delay and current slew rate regulation scheme for AGDs for paralleling SiC metal-oxide-semiconductor field-effect-transistor (MOSFET) power modules is proposed in this article. The advantage of the proposed scheme is that it achieves independent closed-loop control for the delay regulation and the current slew rate regulation, i.e., the adjustment of the current slew rate will not affect the already-tuned delay compensation. Also, the proposed AGD based on gate resistance adjustment with just two push-pull driver channels and less switching actions can achieve the wider-range and multilevel current slew rate regulation. Experimental validation of the closed-loop current regulation for current sharing between SiC power modules with the presented AGD is provided.

关键词： Thermal effects   Ballistic transport   Drift-diffusion   Time delay   Thermoelectric transport  

摘要： With the size down and integration of power devices, the internal thermal management problem has become particularly severe. Especially in the channel region, significant heat generation can lead to a rapid increase in device temperature, which not only exacerbates the degradation of electrical performance in the channel region but also poses a severe threat to the overall reliability and stability. The drift-diffusion (D-D) transport method is employed to calculate the dynamic heat generation of n-MOSFET power devices, and the effects of size and electrical parameters on the thermal production mechanism are analyzed. Considering the quasi-ballistic effect of carrier transport in nanoscale devices, the ballistic diffusion equation (BDE) is introduced to calculate the heat transfer characteristics, and the temperature distribution is explored. The results show that, under a given input voltage, the heat accumulation due to short-channel effects becomes more pronounced with the Kn increase, forming high-temperature hotspots between the gate and drain. When the scale shrinks further ( Kn = 5 and Kn = 10), energy accumulation will occur between the gate and source, increasing temperature rise. At smaller scales, the thermal production on each side of the gate increases with the rise of the conduction voltage, especially under the working condition of Kn = 10, V g = V d = 1.0 V. Moreover, heat production and temperature transfer have a significant time delay. Specifically, it takes 15 fs for heat generation to reach a stable state, while the stable transfer of heat takes 12 ps.

关键词： Motors   Filters   Voltage control   Switches   Inductors   Motor drives   Transient analysis   Switching loss   MOSFET   dv/dt profiling   auxiliary L filter   drive-side overcurrent   motor-side overvoltage   reflected wave phenomenon (RWP)   silicon carbide (SiC)   split-phase topology (2L-SP)   split-phase topology (2L-SP)  

摘要： Fast switching speed of silicon carbide (SiC) exacerbates reflected wave phenomenon (RWP) in two-level (2L) voltage source inverter (VSI)-based motor drives, causing motor side overvoltage and drive side overcurrent. The 2L split-phase (2L-SP) topology shows prospects of alleviating RWP due to its lower output dv/dt facilitated by split-inductors which also serve as an output reactor. This article explores RWP in a 2L-SP-based motor drive and compares it with the 2L with an output reactor, denoted as 2L-LF. For the study, a 2L, 2L-LF, and 2L-SP configurable 18-kVA SiC-based prototype is developed and interfaced to an emulated motor load through a bundled shielded cable. At first, simplified lumped differential mode (DM) equivalent circuits are derived for modeling RWP transients in 2L-LF and 2L-SP drives. Subsequently, RWP is investigated through double pulse tests (DPT) for various cable lengths, reactor (2L-LF), and split inductor (2L-SP) values. Results show that 2L-SP exhibits lower RWP for longer cables, achieving up to 68% and 73% reduction in overvoltage and overcurrent amplitudes for an 8 m cable. An anomalous rising overvoltage pattern for short cables is observed for both drive configurations and analyzed using proposed DM equivalent circuits. Further, from a switching performance standpoint, split-inductors in 2L-SP decouple load and complementary cell's parasitics from the device during switching, achieving 17% lower switching loss than 2L-LF. Following the DPTs, continuous three-phase tests are performed for 8 m cable for both drive configurations. The 2L-SP drive achieves up to 60% and 74% reduction in overvoltage and overcurrent amplitudes than 2L-LF. Overall, 2L-SP outperforms 2L-LF in mitigating RWP in SiC-based 2L VSI motor drives.

关键词： Silicon carbide   MOSFET   Temperature measurement   Delays   Logic gates   Temperature sensors   Time measurement   Sensitivity   Junctions   Accuracy   Junction temperature   medium voltage   reliability   silicon carbide (SiC) MOSFET  

摘要： This letter introduces a novel nonintrusive high-accuracy online junction temperature (T-j) measurement method for medium-voltage SiC mosfets based on the passive turn-on delay time (t(d,on)) integrator. Different from previous studies, the proposed passive t(d,on) integrator-based method can achieve high-accuracy online T-j measurement without the need for large gate resistance. Furthermore, it tends to track the highest T-j of all the chips in the multichip power module. Finally, experiments performed on a self-developed 3.3-kV half-bridge SiC mosfet module validate the effectiveness of the proposed method. The experimental results show that the proposed method can accurately monitor T-j of 3.3-kV SiC mosfets with a small error of less than 3 degrees C and a temperature sensitivity of 11.07 mV/degrees C.

关键词： NCDGMOSFET   junction-less   ferroelectric material   negative capacitance   subthreshold performance  

摘要： The major focus on any transistor-level design is to minimize the effects on switching speed and power consumption at smaller dimensions, which are crucial in VLSI design for low power applications. In this work, a double gate MOSFET design is proposed with p+ pocket in the channel region at 10 nm technology node. Further a ferroelectric material HfO2FE is also introduced between gate and oxide layer resulting a negative capacitance double gate MOSFET (NCDGMOSFET). Ferroelectric material shows negative capacitance that limits the subthreshold slope with dimension scaling. Increased gate control and high switching speed in NCDGMOSFET with lightly doped n-channel, is a promising transistor option for low-power high performance IC design. The proposed device design is characterised with different pocket dimensions for gate and drain voltage ranges from 0 V to 1.5 V. The contact resistance of drain and source is also varied to observe device ON/OFF performances. The electrostatic behaviour of the device is also analysed via observation of electric field and potential variations at different bias conditions. Adding a p+ pocket in the NCDGMOSFET structure further enhances the performance by modifying the channel properties with subthreshold slope and DIBL vales of 76 mV decade-1 and 36 mV/V respectively. This modification also leads to improved barrier to subthreshold conduction during the Ioff state of the transistor, while minimally impacting the Ion state. The proposed device design and performance analysis are conducted through TCAD 2D/3D device simulation software by Cogenda.

关键词： beta-Ga2O3   NiO   MOSFET   current blocking layer   enhancement  

摘要： To address the challenges of P-type doping in beta-Ga2O3 material and the low breakdown voltage of junctionless MOSFETs, this study introduces the first investigation of a vertical enhanced heterojunction beta-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) with a NiO current blocking layer (CBL), employing the Sentaurus TCAD software. The results demonstrate that by adjusting the thickness and concentration of the CBL and epitaxial layers, the threshold voltage of the device oscillates between 2.8 V and 5.1 V, and the enhancement structure is successfully realized. The optimised device exhibits a current switching ratio exceeding 109, a specific on-resistance (Ron,sp) of 9.01 m Omegacm2, a breakdown voltage of 6061.6 V, and a power figure of merit as high as 4.08 GW cm-2. This work is instructive for the design of NiO/beta-Ga2O3 heterojunction enhanced vertical MOSFET power devices and for the future development of beta-Ga2O3 heterojunction power devices.

关键词： 广义互模糊函数   积分旁瓣电平   最大块改进   连续凸近似   交替方向惩罚法  

摘要： 具有良好相关特性的正交波形集可以提高多输入多输出(MIMO)雷达系统的目标检测性能和抗干扰能力。为此，该文提出主瓣增益和动态范围约束下最小化广义互模糊函数积分旁瓣(ISL)的发射序列集和接收滤波器组联合设计方法。该方法采用最大块改进算法(MBI)将非凸优化问题分解为多个子问题，再利用连续凸近似方法(SCA)迭代求解子问题。为了进一步降低运算量，该文还提出了具有并行实现潜力的交替方向惩罚法(ADPM)求解SCA的子问题。最后，通过仿真实验从收敛速度、积分旁瓣电平等方面验证了该方法的有效性。