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关键词： Nanoprobing   MOSFET   Heavy doping missing defect   SCM  

摘要： The paper demonstrates an effective flow to localize heavy doping missing defect accurately in failed metaloxide-semiconductor field-effect transistor (MOSFET). It is commonly known that it is not feasible to localize rare doping anomaly and further visualize the corresponding less doped regions in MOSFET relying on ordinary transmission electron microscopy (TEM) analysis since the dopant distribution is not detectable for TEM. Nevertheless, we found that this kind of defect can be isolated by the combined use of nanoprobing analysis and scanning capacitance microscopy (SCM) technique. The combinational solution was rarely reported before. Nanoprobing analysis of transfer characteristic of failed MOSFET confirms the on-state current drop by two orders of magnitude. Next, the contacting state at source and drain region of MOSFET is examined. Currentvoltage (I-V) characteristic of source and drain p-n junctions indicates that high contact resistance comes from metal-semiconductor interface change from ohmic contact to rectifying contact unexpectedly. Eventually, intensive analysis of SCM data proves that tungsten plugs touch lightly doped silicon so that the outcome leads to the formation of Schottky junction that owns rectifying I-V characteristic. In contrast, the tungsten plug touching heavily doped silicon produces ohmic contact, so it keeps normal I-V characteristic of p-n junction. Energy-band theory explains that I-V characteristic of metal-semiconductor interface is closely related to doping concentration in silicon since it determines the potential barrier width at interface where mobile carrier transport phenomenon occurs. The potential barrier width increases as the doping concentration decreases in the silicon side of the interface. We conclude that lack of heavy doping in MOSFET source and drain areas is responsible for high contact resistance. In the article, we present several practical examples to show accurate localization of heavy doping missing defe

关键词： Logic gates   Inductance   Threshold voltage   MOSFET   Silicon carbide   Resistance   Aging   Transient analysis   Switches   Stress   Asymmetric layout   current sharing   parallel connection   silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs)   stray inductance   threshold voltage  

摘要： For high-capacity applications, paralleling multiple silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfets) is essential. However, it is challenging to achieve complete symmetry in the gate circuits of parallel devices, resulting in mismatched gate inductances, which may lead to the current imbalance. This article focuses on investigating the evolution of threshold voltage dispersity under mismatched gate inductances and its impact on the current sharing evolution. It is found that mismatched gate inductances cause the threshold voltage dispersity to increase with gate stress time, thereby inducing a deterioration in current sharing. A boost converter with two devices in parallel was tested, demonstrating that the difference in the minimum turn-off gate voltage including undershoot is the primary trigger for increased threshold voltage dispersity. Besides, an off-state gate voltage optimization strategy was proposed to effectively mitigate the increase in threshold voltage dispersity and improve the evolution of current sharing under mismatched gate loop inductances. The findings are intended to improve the performance of SiC mosfets in parallel applications.

关键词： Negative capacitance   Double-gate MOSFET   Subthreshold swing   Linearity  

摘要： The negative capacitance metal-oxide-semiconductor field-effect transistor (NC-MOSFET) has gained significant attention for its potential in low-power applications. This paper introduces a novel triple-material double-gate negative capacitance MOSFET (TM-DG-NC-MOSFET) architecture, analyzed through technology computer-aided design (TCAD) simulations to assess its DC, analog, linearity, and distortion performance characteristics. For comparison, a triple-material double-gate MOSFET (TM-DG-MOSFET) without the negative capacitance effect is also designed and simulated. Key device parameters are optimized for both architectures. TCAD simulation results at VDS = 0.1 V reveal that the TM-DG-NC-MOSFET achieves a subthreshold swing of 25 mV/decade, an on-state current of 3.19 x 10-3 A/mu m, and a switching ratio of 5.13 x 107, outperforming the baseline TM-DG-MOSFET, which exhibits a subthreshold swing of 77 mV/decade, an on-state current of 0.83 x 10-3 A/mu m, and a switching ratio of 1.34 x 107. Comparative analysis shows that the TM-DG-NC-MOSFET offers enhanced DC, analog, and linearity performance with reduced distortion, indicating its suitability as a promising candidate for low-power circuit applications.

关键词： MOSFET   Logic gates   Switching loss   Resistance   Capacitance   Voltage   Switching frequency   Switches   Transient analysis   Internet of Things   Analog-digital integrated circuits   DC-DC power converters   Low power electronics   Monolithic integrated circuits   Power MOSFET   Power system management   Power integrated circuits   PMICs   Switched mode power supplies  

摘要： This article presents a novel mixed-signal architecture for the extraction and online tracking of the maximum efficiency point in generic integrated dc-dc converters, called power segmentation optimum. This optimal condition is achieved by dynamically adjusting the size of the power switches to minimize total losses. Proposed system continuously tracks the optimal efficiency point under all operating conditions, adapting to both external factors (such as input/output voltage, switching frequency, temperature, and output current) and internal parameters (such as mosfet on-resistance, and gate capacitance). The operating principle consists in a A/D mixed signal implementation which continuously extracts and compares a proportional value of each loss contribution, deriving the corresponding configuration which minimizes the total losses. This technique is particularly suitable for IoT applications, characterized by long idle periods and high current pulse transients. In order to validate the theoretical results, proposed method is implemented inside a 5 A dc-dc fullyintegrated buck converter realized in 180 nm technology with 5 V input voltage rating and switching frequency up to 4 MHz.

关键词： Transistors   Logic gates   Voltage measurement   Semiconductor device modeling   HEMTs   Gallium nitride   Capacitance   Silicon   MOSFET   Switching circuits   Gallium nitride (GaN) devices   hybrid-drain-embedded gate injection transistor (HD-GIT)   behavioral model  

摘要： Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs), with their superior on-resistance and switching times, provide a promising alternative to Silicon (Si) and SiC devices. Commercially available normally offGaN transistors can be categorized into two main groups: hybrid transistors, which incorporate a Si mosfet, and e-mode transistors. The latter are the most promising GaN transistors, as they do not have the limitations of Si mosfets. Currently, there are two commercial e-mode transistors: the Schottky Gate (SG) p-GaN and the HD-GIT (Hybrid-Drain-embedded Gate Injection Transistor) transistors. However, they differ from the gate terminal standards that have been defined for years by Silicon IGBTs and mosfets (lower threshold voltage, nonconstant Miller plateau, etc.), complicating their adoption in power electronics converters. This is particularly true for the HD-GIT transistor, which diverges from standard mosfet gate operations due to its nonisolated gate terminal. To aid application engineers in understanding these devices and facilitating their adoption in real power applications, simulation models are useful tools. However, there are no simple HD-GIT transistor models that can be easily parameterized by application engineers. Therefore, in this work, an experimentally verified behavioral model of an HD-GIT transistor is presented and described.

关键词： Chua's diode   Chua's circuit   MOSFET   Chua's attractors   Hidden attractor   Secure communication  

摘要： This research work contributes a Chua's circuit design using only two Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) based Chua's diode. This design enables the following advantages like: (i) Use of a minimum number of transistors, (ii) Absence of passive components in Chua's diode, (iii) High packaging density with 108.9 mu m2 chip area, (iv) Suitable for the generation of all fundamental bifurcation sequences. The workability of the circuit is verified using Cadence's Virtuoso tool with gpdk 180 nm technology parameters, along with the process, biasing (bias current), and temperature variation analysis. Moreover, an experimental validation is performed using commercially available N-MOSFET (2N7000). The proposed design is suitable for Chaotic-Amplitude-Shift-Keying (CASK) transmission for secure communication. At end, a comparative analysis is done with the available Chua's circuit.

关键词： Logic gates   Switches   Three-dimensional displays   HEMTs   Integrated circuit interconnections   JFETs   Control systems   Voltage control   Silicon carbide   MOSFET   SiC JFET   GaN HEMT   3-D package   switching speed  

摘要： To unlock the full fast-switching potential of the GaN-HEMT/SiC-JFET cascode device, parasitic interconnection inductances are minimized with a 3-D stacked co-packaging configuration. This configuration offers the benefits of reduced switching loss and suppressed oscillation. Equipped with the 3-D co-package configuration, the dv/dt control capability of the GaN/SiC cascode device is enhanced by introducing an additional gate-drain capacitor, CGD-LV, to the low-voltage GaN HEMT. This additional CGD-LV improves the coupling between the input control gate voltage and the JFET's gate voltage, which ultimately determines the switching speed of the GaN/SiC cascode device. Experimental results verified the GaN/SiC cascode device, when equipped with the 3-D co-packaged configuration and the additional CGD-LV, demonstrated fast switching capability with adequate dv/dt control.

关键词： characterization of the effect   junction temperature monitor   SiC MOSFET   turn-off voltage spike  

摘要： Because of the advantages of high switching speed, silicon carbide (SiC) devices are widely used in high-power power electronic equipment. Real-time monitoring of junction temperature is very important for the safe operation of equipment. There have been many studies on traditional junction temperature monitoring methods based on Si IGBT, but the dynamic characteristics of SiC MOSFETs are changed due to their different physical structure and parasitic parameters, which make the traditional methods no longer applicable. In this paper, the junction temperature can be extracted from the switching process of SiC MOSFET by using the turn-off voltage spike as the index of thermosensitive electrical parameter (TSEP). In addition, the effect of working voltage, current, and different materials on turn-off voltage spike is also studied. The simulation platform of Ansys/Simplorer and the experimental test platforms are built, and the theory of junction temperature detection based on turn-off voltage spike is verified. The simulation and experimental results show that turn-off voltage spike is a feasible TSEP, which can be used to extract junction temperature of SiC MOSFET with good linearity and instantaneity. This paper proposes a junction temperature measurement method applied to SiC modules. The method is based on the derivation of the turn-off voltage spike to the junction temperature of the SiC device. The turn-off voltage spike method has better accuracy as well as stability compared to the conventional method. image

关键词： Voltage   Inductors   Capacitors   Topology   MOSFET   Voltage measurement   Transient response   Buck-boost   dc-dc converter   fast transient response   flying capacitor   hybrid converter   lithium-ion (Li-ion) battery   no right-half-plane zero   switched capacitor   three-fine-level buck-boost (3FLBB)  

摘要： This article presents a non-inverting three-fine-level buck-boost (3FLBB) hybrid converter suitable for lithium-ion (Li-ion) batteries. With seven power switches and two flying capacitors, the proposed 3FLBB converter produces the voltage of switching node between V-IN/2, V-IN , and 3 V-IN /2, which supports buck, boost, and buck-boost modes, and with smooth mode changes. Here, one of the two flying capacitors is used to drive the inductor (L), while another one is used to ensure that V-DS of each power switch is within 1/2V(IN) in all phases. Hence, the voltage stress of all the power switches is reduced to half-V-IN, and the normalized equivalent resistance and switching losses are greatly reduced by using two 1.8-V switches instead of two 5-V switches. Since the three modes all have buck-like operation, the average inductor current is reduced to always equal to the output current. Meanwhile, they all have continuous output current, similar complex pole pairs, and no right half-plane (RHP) zero, which enables fast load transient response. This design is implemented by only 1.8-V devices of a standard 0.18-mu m CMOS process, covering an input voltage range from 2.8 to 4.2 V. A 98.2% peak efficiency is measured at 2-MHz switching frequency with 2.2-mu H L, two 10-mu F mu F flying capacitors, and one 10-mu F output capacitor. It can deliver an output current of 50-1000 mA at a 3.3-V regulated output voltage. Moreover, the measured results show that this design achieves a significant improvement on undershoot and overshoot voltage than the previous works.

关键词： Gallium nitride   Cryogenics   Temperature measurement   Breakdown voltage   Silicon   HEMTs   Transistors   Temperature   Silicon carbide   MOSFET   Cryogenic propulsion   cryogenic power electronics   gallium nitride (GaN) HEMT  

摘要： With the growing electrification of aircraft, power electronics is playing an increasingly vital role in driving this transformation. It is expected that some all-electric aircraft will utilize liquid hydrogen as power fuel as well as coolant, which opens the possibility of utilizing cryogenic power electronics that offers higher efficiency and faster switching speeds than its room-temperature counterpart. Literature has shown that the most efficient semiconductor switch at cryogenic temperatures is gallium nitride (GaN). Thus, this article focuses on studying the characteristics of a 650-V GaN transistor at room temperature and cryogenic temperature at 77 K. Forward and breakdown voltage tests are performed to characterize the device. With the extracted device characteristics, a buck converter is simulated to estimate its efficiency and room and cryogenic temperatures.