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关键词： Transistors   MOSFET   Logic gates   Silicon   Photonic band gap   Logic   Green's function methods   2-D material   field-effect transistor (FET)   logical applications   mid-frequency model   non-equilibrium Green's function (NEGF)   quantum transport   tight-binding (TB)  

摘要： A sub-nanometer field-effect transistor (FET) with MoSi(2)N(4 )as the channel material is investigated using non-equilibrium Green's function (NEGF) formalism for possible application in modern digital technology. The transistor input, output, and transfer characteristics are reported for 0.6 V supply. The output and transfer characteristics of the drain current versus the drain-source and gate-source voltages are investigated. The nMOS transistor ON-current is found to be two and a half times greater than that of the pMOS. In addition, the pMOS transistor shows about two orders of magnitudes smaller OFF-current with respect to nMOS, one for short channel length. The low value of I-OFF leads to lower static power, fascinating to digital applications. The BSIM4 model version 4.8 is utilized for extracting the mid-frequency model with a precision of more than 99%. An evident matching between NEGF and Berkeley Short-channel IGFET Model (BSIM) models is observed for the investigated logic.

关键词： integrated circuit manufacture   MOSFET   nanofabrication  

摘要： In this letter, to improve the performance and reduce leakage currents of bulk low-temperature multi-layer SiGe/Si superlattice (SL) fin field-effect transistors (FinFETs), a p-type omega-shaped channel (Omega-channel) SL FinFET is realized by etching a Si/Si0.7Ge0.3 triple-layer stacked structure in a replacement metal gate (RMG) module on a silicon-on-insulator (SOI) substrate. In addition, a self-allied Ni0.9Pt0.1 silicide process and a low-thermal-budget (<= 400 degrees C) integration procedure were performed on the Omega-channel SL FinFET. Test results demonstrate that the on-state current (Ion) is increased by 5.5 times (from 78 to 429 mu A/mu m) and the off-state current (Ioff) is reduced by 78.8% (from 5.2 x 10-3 to 1.1 x 10-3 mu A/mu m) when compared with the corresponding currents of traditional bulk SL FinFETs.

关键词： MOSFET   power MOSFET   Schottky diodes   semiconductor device breakdown   semiconductor devices  

摘要： An improved 4H-SiC SBD-wall-integrated trench metal-oxide-semiconductor (SWITCH-MOS) with n-bury and split-gate is proposed. Under the premise of ensuring breakdown voltage (BV), the n-bury layer can smooth the path to current conduction, which reduces the specific on-resistance (RON, SP) and improves static characteristics. Besides, the split-gate is able to transform the gate-drain capacitance (CGD) and improve the dynamic characteristics. Therefore, a superior forward performance that SWITCH-MOS always craves is achieved. According to the simulation results, compared to the conventional SWITCH-MOS with almost the same BV, the proposed one reduces the RON, SP by 57% and the CGD by 59% while gaining equally advanced reverse performance. Its reverse conduction voltage is only -1.78 V, but its figure of merit reaches 1.67 GW/cm2 and 65 m OmeganC, which is attractive for the application in power inverters.

关键词： Mach-Zehnder interferometers  

摘要： Objective Optical signal processing is widely used in modern communication systems due to its large bandwidth, low loss, and capability for easy parallel transmission. Rectangle filters, as key components in optical signal processing systems, have become a prominent research focus because they meet the requirements of wavelength division multiplexing systems and are well-suited for broadband access applications. Integrated rectangular filters typically use structures such as waveguide gratings (WGs), Mach-Zehnder interferometers (MZIs), and microring resonators (MRRs). Although these designs achieve good performance, they often suffer from drawbacks like large size and complex manufacturing processes. In this paper, we propose an ultra-compact, silicon-based rectangular filter with a high shape factor, which significantly advances the miniaturization of wavelength division multiplexing systems and enhances the performance of elastic optical networks, on-chip optical interconnects, and broadband access systems. Methods Our design utilizes silicon-on-insulator (SOI) technology, where the top silicon layer has a thickness of 220 nm and the buried oxide layer is 2 µm thick. The waveguide is etched to a depth of 220 nm to form a strip waveguide, with an additional 2 µm of SiO2 deposited on top (Fig. 3). The filter consists of a single MRR with a slot fabricated in the resonator, also etched to a depth of 220 nm. By fine-tuning the slot’s length (ls) and width (ws), and the gaps (g1 and g2) between the ring and the straight waveguide, we create an ultra-small rectangle filter. To mitigate the effects of fabrication errors, we incorporate two micro-heaters in the coupling regions of the MRR. The filtering performance is significantly enhanced by adjusting the voltage applied to these heaters. Results and Discussions The gaps between the ring resonator and the input and output waveguides, denoted as g1 and g2 respectively, and the slot dimensions (length ls and width ws) wi

关键词： SiC MOSFET   Reverse conduction   Low switching losses   Bipolar degradation  

摘要： A novel asymmetric trench Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC MOSFET), featuring an integrated channel accumulation diode (CAD-MOS), has been proposed and investigated through numerical simulation. This innovative design aims to mitigate switching losses and eliminate the bipolar degradation of the body diode. The current spreading layer (CSL) channel, strategically positioned in the centre of the dummy gate, offers a low-barrier reverse conduction path. This represents a substantial advancement over the traditional PN body diode, significantly reducing the reverse conduction voltage drop from 2.84 V in the PN body diode to a mere 1.39 V in the CAD-MOS. Meanwhile, the reverse recovery charge of the CAD-MOS is reduced to 0.95 mu C/cm2, and the peak reverse recovery current stands at 45 A/cm2. Compared to conventional asymmetrical trench SiC MOSFET (CON-MOS), the CAD-MOS exhibits a 68.1 % reduction in reverse recovery charge and a 63.4 % decrease in peak reverse recovery current. The split-gate design also reduces the device gate to source capacitance (CGS), resulting in a 17.4 % reduction in total switching losses to 3.64 mJ/cm2. CAD-MOS also exhibits a reduced gate turn-on charge and demonstrates an enhancement in high-frequency figure of merit (HF-FOM) by 8.1 %.

关键词： Reliability   Fault trees   Analytical models   Motors   MOSFET   Hidden Markov models   Sensors   Operation principles   reliability evaluation   reliability model   switched reluctance motor  

摘要： This paper proposes an enhanced k-out-of-n:G model to assess the reliability of the dual-stator switched reluctance motor system (DSSRM). Firstly, the failure rates of power components are calculated as the basis for evaluating the system-level reliability. Then, traditional system-level reliability models, including fault tree and Markov models, are established. Subsequently, the proposed model is established based on the same predefined failure discrimination with Markov model, and the corresponding reliability calculation process is derived. The reliability of power converter in the DSSRM system is quantitatively compared based on the three models. The results indicate that the fault tree model yields overly conservative evaluations. And the proposed model almost maintains same results with the Markov model, and simplifies effectively the modeling and solving process. Finally, the experiments are developed to verify the validity of reliability assessment results.

关键词： Detection   gas spectroscopy   high-bandwidth   Gaussian beam   MOSFET   power coupling   quantum-cascade lasers (QCLs)   terahertz  

摘要： Monolithically integrated, antenna-coupled fieldeffect transistors (TeraFETs) are rapid and sensitive detectors for the terahertz range (0.3-10 THz) that can operate at room temperature. We conducted experimental characterizations of a singlepatch-antenna-coupled TeraFET optimized for 3.4 THz operation and its integration into an 8x8 multielement detector configuration. In this configuration, the entire TeraFET array operates as a unified detector element, combining the output signals of all detector elements. Both detectors were realized using a mature commercial Si-CMOS 65-nm process node. Our experimental characterization employed single-mode quantum-cascade lasers (QCLs) emitting at 2.85 and 3.4 THz. The 8x8 multielement detector yields two major improvements for sensitive power detection experiments. First, the larger detector area simplifies alignment and enhances signal stability. Second, the reduced detector impedance enabled the implementation of a TeraFET+QCL system capable of providing a-3 dB modulation bandwidth up to 21 MHz, which is currently limited primarily by the chosen readout circuitry. Finally, we validate the system's performance by providing high-resolution gas spectroscopy data for methanol vapor around 3.4 THz, where a detection limit of 1.6 x 10(-5) absorbance or 2.6 x 10(11) molecules/cm(3) was estimated.

关键词： MOSFET   Stress   Logic gates   Threshold voltage   Temperature measurement   Semiconductor device measurement   Voltage measurement   Electron traps   Leakage currents   Filling   Deep-level transient spectroscopy (DLTS)   point defects   silicon-based MOSFET chips  

摘要： In this study, the electrical performance and evolution of point defects in chip-level Silicon-based MOSFET under transmission line pulse (TLP) stress were investigated. The experimental results show that the threshold voltage decreased by 9.8%, and the output saturation current increased by 5.9% after the stress. An intrinsic point defect with an energy level of 0.25 +/- 0.05 eV in Si-based MOSFET chips was observed by using deep-level transient spectroscopy (DLTS), which shifted to 0.37 +/- 0.05 eV after the stress. The increase of the trap energy level would reduce the holes at the Si/SiO2 interface, and herein the threshold voltage reduced. This work helps to further understand the evolution of point defects in Si-based MOSFET chips.

关键词： Switching loss   Semiconductor device modeling   Analytical models   Silicon carbide   Hysteresis   Numerical models   Switches   Analytical model   buck   dynamic   switching loss   threshold voltage instability   threshold voltage instability  

摘要： Accurate modeling of switching loss is critical for silicon carbide mosfets as well as power converters. However, previous "static" time-independent models did not consider the impact of gate oxide degradation on switching performance during long-term operation. This article proposes a "dynamic" time-dependent analytical model considering threshold voltage (V-TH) instability caused by gate oxide degradation to predict switching loss. The influence of V-TH instability on the turn-on and turn-off V-TH, as well as on switching loss during continuous operation is revealed first. Moreover, the problems suffered in the existing analytical model are investigated, and an improved switching loss model is presented. A measurement-based method to obtain the V-TH instability parameters for modeling is provided. Furthermore, a buck converter is built and operated under different conditions. Comparisons of switching waveforms and switching losses between experiments and the proposed model are given to validate the model. The results indicate that the proposed analytical model can effectively evaluate the switching loss, with an error within 7% under different continuous operating conditions. Finally, the universality of the proposed model for devices with different structures is verified, and a predication application of the model in operation is demonstrated.

关键词： MOSFET   Degradation   Logic gates   Silicon carbide   Stress   Insulated gate bipolar transistors   Switches   Degradation location   reliability   short-circuit (SC)   traps   traps  

摘要： Degradation of SiC power mosfets under repetitive short-circuit (SC) stress is significant to the reliability of the power systems. A deep level transient spectrum method together with split C-V method to split the trap characteristics of the SiC mosfets is proposed. The degradation details of different locations in SiC planar gate (PG) and trench gate (TG) mosfets are comprehensively studied in this article. Thus, a criterion is provided to guide the SC degradation from the aspect of traps. The main degradation of the channel region is the increase of border traps for PG mosfet and newly generated interface traps for TG mosfet. The interface traps domain the degradation in the JFET region for both devices. The degradations of gate oxide for both devices affect the channel and JFET regions especially in the first set of SC cycles. The degradation of body diode is mainly influenced by hole traps in PG mosfet, but by electron traps first then hole traps newly generated in TG mosfet. Finally, the degradation locations of PG and TG mosfets are effectively characterized. It is the first time to use the trap measurement method to separate the different degradation in every part of the devices in detail. The method proposed in this article can better reflect the failure mechanisms related to dynamics and evaluate the operation of devices effectively, which provides very useful guidance for the reliability design and utilization of SiC mosfets.